Method of cache prefetching that increases the hit rate of a next faster cache
AssigneeMarvell Asia Pte Ltd
InventorsShay Gal-On, Srilatha Manne, Edward McLellan, Alexander Rucker
Life of this patent
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Abstract
The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.
Claims20
A method of cache prefetching, the method comprising:
- determining whether a cache has received a read request from a next faster cache, the read request including a currently requested memory address;
- determining whether the currently requested memory address is stored in the cache when the read request has been received;
- outputting an entry associated with the currently requested memory address to the next faster cache when the currently requested memory address is stored in the cache;
- determining whether a cache line with the currently requested memory address has a valid short pointer pointing to a predicted next memory address;
- and
- pushing the predicted next memory address and an entry associated with the predicted next memory address to the next faster cache in response to determining that the cache line with the currently requested memory address has the valid short pointer.
A computer system, comprising:
- a memory;
- and
- a processor coupled to the memory to execute instructions stored in the memory, the processor configured to:
- determine whether a cache has received a read request from a next faster cache, the read request including a currently requested memory address;
- determine whether the currently requested memory address is stored in the cache when the read request has been received;
- output an entry associated with the currently requested memory address to the next faster cache when the currently requested memory address is stored in the cache;
- determine whether a cache line with the currently requested memory address has a valid short pointer pointing to a predicted next memory address;
- and
- push the predicted next memory address and an entry associated with the predicted next memory address to the next faster cache in response to a determination that the cache line with the currently requested memory address has the valid short pointer.
A non-transitory computer-readable medium having computer-readable instructions stored thereon which, when executed by a processor, cause the processor to execute a method of cache prefetching, the method comprising:
- determining whether a cache has received a read request from a next faster cache, the read request including a currently requested memory address;
- determining whether the currently requested memory address is stored in the cache when the read request has been received;
- outputting an entry associated with the currently requested memory address to the next faster cache when the currently requested memory address is stored in the cache;
- determining whether a cache line with the currently requested memory address has a valid short pointer pointing to a predicted next memory address;
- and
- pushing the predicted next memory address and an entry associated with the predicted next memory address to the next faster cache in response to determining that the cache line with the currently requested memory address has the valid short pointer.
Dependencies are inferred from the claim text.