US 11,080,190 B2Granted

Detecting and correcting cache memory leaks

AssigneeEMC IP Holding Company LLC

InventorsKaustubh Sahasrabudhe, Steven Ivester

Life of this patent

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Abstract

Embodiments of the present disclosure relate to an apparatus comprising a memory and at least one processor. The at least one processor is configured to monitor one or more processing threads of a storage device. Each of the one or more processing threads includes two or more cache states. The at least one processor also updates one or more data structures to indicate a subject cache state of each of the one or more processing threads and detect an event that disrupts at least one of the one or more processing threads. Further, the processor determines a cache state of the at least one of the one or more processing threads contemporaneous to the disruption event using the one or more data structures and performs a recovery process for the disrupted at least one of the one or more processing threads.

Claims18

Dependent claims

An apparatus comprising a memory and at least one processor configured to:

monitor one or more processing threads of a storage device, wherein each of the one or more processing threads includes at least one processing step that adjusts a state of at least one cache slot;
update one or more data structures to indicate a processing status of each of the one or more processing threads;
update the one or more data structures to indicate the state of the at least one cache slot in response to an execution of the at least one processing step;
detect an event that disrupts at least one of the one or more processing threads;
in response to detecting the event, identify the states of the one or more processing threads and the at least one cache slot using the at least one or more data structures;
and
perform a recovery process for the at least one cache slot by selecting a recovery node including instructions for recovering the cache slot based in the identified states.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/507,442Filed 10 Jul 2019
Published: US 2021/0011850 A114 Jan 2021
Granted: 3 Aug 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 12/0815
Multiuser, multiprocessor or multiprocessing cache systems: cache consistency protocols
G06F 13/1668
For access to memory bus: details of memory controller
G06F 9/3861
Concurrent instruction execution, e.g. pipeline or look ahead: recovery, e.g. branch miss-prediction, exception handling
G06F 9/542
Interprogram communication: event management; Broadcasting; Multicasting; Notifications