Software-invisible interrupt for a microprocessor
AssigneeInternational Business Machines Corporation
InventorsLarry Leitner, John A. Schumann, Debapriya Chatterjee, Wallace Sharp, Bryant Cockcroft
Life of this patent
Estimating the term…
Abstract
Examples described herein provide a computer-implemented method that includes executing, by the microprocessor, instructions in an instruction stream of the microprocessor. The method further includes triggering, by control logic of the microprocessor, error condition monitoring logic. The method further includes executing, by the error condition monitoring logic of the microprocessor, an error instruction stream built into the microprocessor to break the microprocessor out of an error condition.
Claims8
A computer-implemented method for invisible interrupt of a microprocessor, the method comprising:
- executing, by the microprocessor, instructions in an instruction stream of the microprocessor;
- triggering, by control logic of the microprocessor, error condition monitoring logic wherein the error condition monitoring logic is triggered randomly;
- and
- executing, by the error condition monitoring logic of the microprocessor, an error instruction stream built into the microprocessor to break the microprocessor out of an error condition.
A microprocessor comprising:
- an instruction stream for executing instructions;
- control logic for triggering an error condition monitoring logic, wherein the error condition monitoring logic is triggered randomly;
- and
- the error condition monitoring logic for executing an error instruction stream built into the microprocessor to break the microprocessor out of an error condition.
Dependencies are inferred from the claim text.