Information processing with failure detection, apparatus and method

An information processing method in an information processing apparatus including a first processor, a second processor, and a third processor, said information processing method comprising:

• a process, by the first processor, of performing a first process on sensor information, which is obtained from a sensor, thereby to generate first information;
• a process, by the second processor, of performing a second process, which is different from the first process, on the first information, thereby to generate second information;
• a process, by the third processor, of performing a third process corresponding to at least a part of the second process, on the first information, thereby to generate third information;
• and
• a process, by the third processor, of obtaining the second information and of outputting the second information and the third information, wherein
• the first processor is configured to apply additional information to first information on which the third process is to be performed on the third processor, out of the first information,
• the second processor is configured to perform the second process on the first information with the additional information applied, thereby to generate the second information, and is configured to perform a process corresponding to a part of the second process, on the first information with the additional information applied, thereby to generate fourth information, and
• the third processor is configured to perform the process corresponding to the part of the second process, as the third process, on the first information with the additional information applied, thereby to generate the third information, and is configured to obtain the fourth information in addition to the second information and to output the second information, the fourth information, and the third information.

An information processing apparatus comprising:

• a first processor configured to obtain sensor information from a sensor;
• a second processor;
• a third processor;
• a first signal path for signal transmission via said first processor, said second processor, and said third processor;
• and
• a second signal path for signal transmission not via said second processor but via said first processor and said third processor, wherein
• said third processor (i) is configured to obtain a signal processed by said second processor through said first signal path, and (ii) is configured to obtain a signal processed by said first processor through said second signal path and to simulate at least a part of a process on said second processor.