Posted interrupt processing in virtual machine monitor

A method comprising:

• receiving, by an interrupt posting circuit of a processor, an interrupt request directed to a virtual processor (VP) of a virtual machine (VM) executed by a processor core of the processor, wherein the VM is managed by a virtual machine monitor (VMM) executed by the processor core;
• determining, by the interrupt posting circuit, the VP is in an inactive state;
• recording, by the interrupt posting circuit, the interrupt request in a first posted data structure of a plurality of posted data structures, the first posted data structure allocated by the VMM for the VP in main memory coupled to the processor;
• and
• based at least in part on the recording of the interrupt request in the first posted data structure, updating, by the interrupt posting circuit, location information stored in reporting data structures of a processor cache of the processor to generate updated location information that identifies a location of the interrupt request in the plurality of posted data structures.

A system comprising:

• a memory storing a plurality of posted data structures including a first posted data structure;
• a processor coupled to the memory, wherein the processor comprises:
• a processor core;
• a processor cache to store reporting data structures comprising a queue structure;
• and
• an interrupt posting circuit to:
• receive an interrupt request directed to a virtual processor (VP) of a virtual machine (VM) executed by the processor core, wherein the VM is managed by a virtual machine monitor (VMM) executed by the processor core, wherein the first posted data structure is allocated by the VMM for the VP;
• determine the VP is in an inactive state;
• record the interrupt request in the first posted data structure;
• and
• based at least in part on recording the interrupt request in the first posted data structure, update location information stored in the reporting data structures to generate updated location information that identifies a location of the interrupt request in the plurality of posted data structures.

A processor comprising:

• a processor core to, responsive to receiving one or more requests:
• allocate, in main memory coupled to the processor, a plurality of posted data structures comprising a corresponding posted data structure for each virtual processor (VP) executed by the processor core, wherein each posted data structure comprises a corresponding interrupt-arrived bit;
• and
• responsive to determining that a first condition has occurred in the processor, identify a location of an interrupt request in a first posted data structure by reading the corresponding interrupt-arrived bit of each corresponding posted data structure in the main memory.