Address manipulation using indices and tags
AssigneeMIPS Tech, LLC
InventorsParthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
Life of this patent
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AssigneeMIPS Tech, LLC
InventorsParthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
Estimating the term…
Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N−1), and the branch history in table T(N−1) is of greater length than the branch history of table T(N−2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
A processor-implemented method for address manipulation comprising:
A computer program product embodied in a non-transitory computer readable medium for address manipulation, the computer program product comprising code which causes one or more processors to perform operations of:
A computer system for address manipulation comprising:
Dependencies are inferred from the claim text.