Reducing firmware size and increasing firmware performance

A method, comprising:

• converting a set of core timing control conditions of a die controller into a set of production ready core timing control conditions for the die controller;
• generating a set of firmware instructions based on the set of production ready core timing control conditions;
• replacing two or more short firmware instructions of the set of firmware instructions with a long firmware instruction;
• configuring a core timing control condition machine to automatically move a subroutine result to a condition value buffer, in response to the core timing control condition machine initiating execution of a subsequent subroutine;
• modifying a firmware instruction that references a common core timing control condition within a common subroutine, such that the firmware instruction re-uses a value for the common core timing control condition, the value stored in a common subroutine result register;
• modifying a first firmware instruction of a first subroutine for a storage operation to store a repeated core timing control condition in a local condition register and modifying a second firmware instruction of a second subroutine for the storage operation to reference a value for the repeated core timing control condition from the local condition register;
• wherein the set of production ready core timing control conditions comprises a plurality of fixed core timing control conditions;
• modifying the set of firmware instructions such that the set of firmware instructions:
• determines core timing control condition values for the plurality of fixed core timing control conditions before implementing storage operations;
• stores the core timing control condition values in one or more global condition registers;
• and
• modifies references to the plurality of fixed core timing control conditions to access the core timing control condition values stored in the one or more global condition registers;
• modifying the set of firmware instructions such that each subroutine references the common subroutine result register and the core timing control machine automatically changes an output register associated with the common subroutine result register in response to the core timing control machine transitioning from executing the first subroutine to executing the second subroutine;
• replacing repeating firmware instructions in the second subroutine with a call instruction to corresponding firmware instructions in the first subroutine;
• and
• wherein a core timing control machine is configured to change a control signal value to a set_reset value in response to a corresponding core timing control condition evaluating to true and to retain the control signal value in response to the corresponding core timing control condition evaluating to false.

An apparatus, comprising:

• non-volatile memory array comprising a plurality of control signals configured to perform storage operations based on settings for the plurality of control signals;
• an instruction buffer configured to store a set of firmware instructions such that one or more pairs of firmware instructions of the set of firmware instructions each share a common address within the instruction buffer;
• a first core timing control machine configured to execute one firmware instruction of a first pair of firmware instructions to determine control signal values for the plurality of control signals, the first core timing control machine further configured to set the determined control signal values in a control signal setting buffer;
• a second core timing control machine configured to execute a second firmware instruction of the pair of firmware instructions in parallel to determine control signal values for the plurality of control signals, the second core timing control machine further configured to set the determined control signal values in the control signal setting buffer;
• and
• a clock configured to operate the first core timing control machine and the second core timing control machine concurrently, each of the first core timing control machine and the second core timing control machine alternately executing time segments of a storage operation.