Processing device and method of controlling processing device

A processing device comprising:

• an instruction decode circuit including a plurality of decoders configured to decode instructions respectively assigned an instruction number that is determined for every one of the plurality of decoders;
• an instruction execution circuit configured to execute the instructions decoded by the instruction decode circuit;
• an instruction complete holding circuit including a plurality of hold blocks provided in correspondence with each of the plurality of decoders and respectively including a plurality of hold regions, wherein the instruction number is assigned to each of the plurality of hold regions, and used for an instruction complete process;
• and
• an instruction complete controller configured to store instruction information that is generated by decoding the instructions by the plurality of decoders, in one of the plurality of hold regions of the hold block corresponding to a decoder that decodes the instruction, based on the instruction number, and obtain, in order, the instruction information corresponding to the instructions executed by the instruction execution circuit from the instruction complete holding circuit, to perform the instruction complete process,
• the instruction decode circuit regards an instruction number that cannot be assigned to the instruction as an unused number, in a case where one of the plurality of decoders does not decode the instruction.

A processing device comprising:

• an instruction decode circuit including a plurality of decoders configured to decode instructions respectively assigned an instruction number that is determined for every one of the plurality of decoders;
• an instruction execution circuit configured to execute the instructions decoded by the instruction decode circuit;
• an instruction complete holding circuit including a plurality of hold blocks provided in correspondence with each of the plurality of decoders and respectively including a plurality of hold regions, wherein the instruction number is assigned to each of the plurality of hold regions, and used for an instruction complete process;
• and
• an instruction complete controller configured to store instruction information that is generated by decoding the instructions by the plurality of decoders, in one of the plurality of hold regions of the hold block corresponding to a decoder that decodes the instruction, based on the instruction number, and obtain, in order, the instruction information corresponding to the instructions executed by the instruction execution circuit from the instruction complete holding circuit, to perform the instruction complete process,
• the instruction decode circuit includes a number of decoders, that is 3 or more but excludes 2n, where n is an integer greater than or equal to 1, and
• the instruction number is assigned to the plurality of hold regions by assuming the number of decoders as being 2n, and regarding the instruction number assigned to the instruction that is assumed to be decoded by a decoder that does not exist as an unused number.

A method of controlling a processing device which includes an instruction decode circuit including a plurality of decoders decoding instructions, an instruction complete holding circuit including a plurality of hold regions assigned an instruction number, and used for an instruction complete process, the method comprising:

• determining an instruction number for every one of the plurality of decoders;
• including, in the instruction complete holding circuit, a plurality of hold blocks respectively including the plurality of hold regions provided in correspondence with each of the plurality of decoders;
• storing, by an instruction complete controller of the processing device, instruction information that is generated by decoding the instructions by the plurality of decoders, in one of the plurality of hold regions of the hold block corresponding to a decoder that decodes the instruction, based on the instruction number;
• and
• obtaining, in order, by the instruction complete controller, the instruction information corresponding to the instructions executed by the instruction execution circuit from the instruction complete holding circuit, to perform the instruction complete process;
• assigning, by the instruction decode circuit, a group number in correspondence with a plurality of instruction numbers assigned to the instruction for every cycle, and outputting the assigned group number to the instruction complete controller together with the instruction information generated by the plurality of decoders;
• and
• storing, by the instruction complete controller, the instruction information received from the instruction decode circuit in a hold region assigned the instruction number corresponding to the group number, among the plurality of hold regions of the hold block.