Deep vision processor
AssigneeDeep Vision Inc.
InventorsWajahat Qadeer, Rehan Hameed
Life of this patent
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Abstract
Disclosed herein is a processor for deep learning. In one embodiment, the processor comprises: a load and store unit configured to load and store image pixel data and stencil data; a register unit, implementing a banked register file, configured to: load and store a subset of the image pixel data from the load and store unit, and concurrently provide access to image pixel values stored in a register file entry of the banked register file, wherein the subset of the image pixel data comprises the image pixel values stored in the register file entry; and a plurality of arithmetic logic units configured to concurrently perform one or more operations on the image pixel values stored in the register file entry and corresponding stencil data of the stencil data.
Claims20
A processor comprising:
- a banked register file:
- comprising a set of register banks;
- configured to store image pixel data within the set of register banks;
- and
- representing a two-dimensional register abstraction;
- an interconnect unit in communication with the banked register file, the interconnect unit configured to:
- concurrently access multiple subsets of the image pixel data from the banked register file, each subset of the image pixel data defining a smaller stencil pattern in a set of smaller stencil patterns, the set of smaller stencil patterns combining to define a larger two-dimensional stencil pattern within the two-dimensional register abstraction;
- and
- concurrently access corresponding stencil data defining the larger two-dimensional stencil pattern;
- and
- a set of arithmetic logic units in communication with the interconnect unit configured to concurrently execute a set of operations on each subset of the image pixel data and the corresponding stencil data, the set of operations representing a larger stencil operation characterized by the larger two-dimensional stencil pattern.
A processor comprising:
- a shift register unit:
- configured to store image pixel data;
- and
- representing a two-dimensional register abstraction;
- and
- a mapping unit in communication with the shift register unit:
- configured to concurrently access multiple subsets of the image pixel data from the shift register unit, each subset of the image pixel data defining a smaller stencil pattern in a set of smaller stencil patterns, the set of smaller stencil patterns combining to define a larger two-dimensional stencil pattern within the two-dimensional register abstraction;
- configured to concurrently access corresponding stencil data for each subset of the image pixel data in the multiple subsets of the image pixel data;
- and
- comprising a set of arithmetic logic units configured to concurrently execute a set of operations on each subset of the image pixel data and the corresponding stencil data, the set of operations representing a larger stencil operation characterized by the larger two-dimensional stencil pattern.
A register unit of a processor core:
- comprising a set of register banks;
- configured to store image pixel data in the set of register banks;
- representing a two-dimensional register abstraction;
- and
- configured to provide access to multiple subsets of the image pixel data in the set of register banks, each subset of the image pixel data defining a smaller stencil pattern in a set of smaller stencil patterns, the set of smaller stencil patterns combining to define a larger two-dimensional stencil pattern within the two-dimensional register abstraction.
Dependencies are inferred from the claim text.