Register file arbitration

A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:

• a register file configured to store operands for multiple client circuits;
• arbitration circuitry configured to select from among multiple received requests to access the register file;
• first interface circuitry configured to store access requests from a first client circuit in first buffer circuitry and provide requests from the first buffer circuitry to the arbitration circuitry via a first input to the arbitration circuitry;
• and
• supplemental interface circuitry configured to receive unsuccessful requests from the first client circuit, store received requests in second buffer circuitry, and provide requests from the second buffer circuitry to the arbitration circuitry via a second input to the arbitration circuitry;
• wherein the arbitration circuitry is configured to select from among requests received from the first interface circuitry, the supplemental interface circuitry, and interface circuitry for one or more other client circuits.

A method, comprising:

• storing, by a register file, operands for multiple client circuits;
• providing, by first interface circuitry to arbitration circuitry from first buffer circuitry via a first input to the arbitration circuitry, a first request to access the register file from a first client circuit;
• storing the request in second buffer circuitry, by supplemental interface circuitry, in response to rejection of the first request by the arbitration circuitry;
• providing, by the supplemental interface circuitry to the arbitration circuitry in a subsequent clock cycle, the first request via a second input to the arbitration circuitry;
• and
• selecting, by the arbitration circuitry, the first request provided by the supplemental interface circuitry, in parallel with a second request to access the register file from the first client circuit, wherein the second request is provided by the first interface circuitry via the first input.