US 11,080,051 B2 · Techniques for efficiently transferring data to a processor

Abstract

A technique for block data transfer is disclosed that reduces data transfer and memory access overheads and significantly reduces multiprocessor activity and energy consumption. Threads executing on a multiprocessor needing data stored in global memory can request and store the needed data in on-chip shared memory, which can be accessed by the threads multiple times. The data can be loaded from global memory and stored in shared memory using an instruction which directs the data into the shared memory without storing the data in registers and/or cache memory of the multiprocessor during the data transfer.

Claims26

Dependent claims

A method performed by a processing system including a multithreaded processor and on-chip memory including a cache memory and a shared memory managed by software, the method comprising:

concurrently executing a plurality of threads including a thread executing a fused load and store instruction to load data stored in a memory external to the processing system and store the data into the shared memory, the fused load and store instruction configurable between bypassing (1) processor registers associated with the thread executing a fused load and store instruction or (2) the processor registers and the cache memory,
wherein the instruction directs the system to:
retrieve the data from the external memory;
and
store the retrieved data into the shared memory without first storing the retrieved data in the processor registers or without first storing the retrieved data in the processor registers and the cache memory.

2 more elements

A method performed by a processing system including:

a multithreaded processor configured to concurrently execute a plurality of threads;
a plurality of registers assigned to the executing threads;
hardware managed cache memory configured to allow the plurality of executing threads to access tagged data stored in the cache memory;
and software managed shared memory configured to allow the plurality of executing threads to access untagged data stored in the shared memory, the method comprising:
concurrently executing a plurality of threads, at least one of the threads executing an instruction to load data stored in a memory external to the processing system and store the data into the shared memory, the instruction configurable to (1) store the data into the shared memory without first storing the data into registers assigned to the executing threads, or (2) store the data into the shared memory without first storing the data into the registers and the cache memory;
in response to the instruction configured to store the data into the shared memory without first storing the data into the registers, retrieving the data from the external memory and storing the retrieved data into the shared memory without first storing the retrieved data in the registers;
and
in response to the instruction configured to store the data into the shared memory without first storing the data into the registers and the cache memory, retrieving the data from the external memory and storing the retrieved data in the shared memory without first storing the retrieved data in the registers and the shared memory.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/712,083Filed 12 Dec 2019 · us provisional application

Priority

29 Oct 2019

Published

US 2021/0124582 A129 Apr 2021

Granted

3 Aug 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

G06F 9/30043
To perform operations on memory: lOAD or STORE instructions; Clear instruction
G06F 9/3009
To perform miscellaneous control operations, e.g. NOP: thread control instructions
G06F 9/321
Address formation of the next instruction, e.g. by incrementing the instruction counter: program or instruction counter, e.g. incrementing
G06F 9/3838
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: dependency mechanisms, e.g. register scoreboarding

Techniques for efficiently transferring data to a processor

Life of this patent

Techniques for efficiently transferring data to a processor

Life of this patent

Abstract

Claims26