Systems, methods, and apparatus for tile configuration

A method comprising:

• decoding an instruction having fields for an opcode and a memory address, the opcode to indicate execution circuitry is to load a tile configuration stored at the memory address, the tile configuration information to at least specify a first and a second dimension for a two-dimensional data structure tile;
• and
• executing the decoded instruction to load the tile configuration for the processor to utilize tiles in matrix operations.

A non-transitory machine-readable medium storing an instruction which causes a processor to perform a method, the method comprising:

• decoding an instruction having fields for an opcode and a memory address, the opcode to indicate execution circuitry is to load a tile configuration stored at the memory address, the tile configuration information to at least specify a first and a second dimension for a two-dimensional data structure tile;
• and
• executing the decoded instruction to load the tile configuration for the processor to utilize tiles in matrix operations.