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US 11,080,047 B2Granted
Register file structures combining vector and scalar data with global and local accesses
AssigneeTexas Instruments Incorporated
InventorsTimothy David Anderson, Due Quang Bui, Mel Alan Phipps, Todd T. Hahn, Joseph Zbiciak
Life of this patent
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Abstract
The number of registers required is reduced by overlapping scalar and vector registers. This allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are reduced by restricting read access. Dedicated predicate registers reduce requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit.
Claims18
A semiconductor device comprising:
- a first execution unit having a first data width;
- a second execution unit having a second data width that is different from the first data width;
- a first local register file including a first plurality of local registers, wherein:
- each of the first plurality of local registers is configured to provide data having the first data width in a first mode of operation and to provide data having the second data width in a second mode of operation;
- and
- the first local register file is coupled to the first and second execution units and configured so that the first and second execution units can write to the first plurality of local registers, the first execution unit can read from the first plurality of local registers, and the second execution unit cannot read from the first plurality of local registers;
- and
- a second local register file including a second plurality of local registers, wherein the second local register file is coupled to the first and second execution units and configured so that the first and second execution units can write to the second plurality of local registers, the second execution unit can read from the second plurality of local registers, and the first execution unit cannot read from the second plurality of local registers.
5 more elements
A semiconductor device comprising:
- a first execution unit;
- a second execution unit;
- a first local register file including a first plurality of local registers, wherein the first local register file is coupled to the first and second execution units and configured so that the first and second execution units can write to the first plurality of local registers, the first execution unit can read from the first plurality of local registers, and the second execution unit cannot read from the first plurality of local registers;
- a second local register file including a second plurality of local registers, wherein the second local register file is coupled to the first and second execution units and configured so that the first and second execution units can write to the second plurality of local registers, the second execution unit can read from the second plurality of local registers, and the first execution unit cannot read from the second plurality of local registers;
- a third execution unit;
- and
- a fourth execution unit;
- wherein the first and second local register files are each additionally coupled to the third and fourth execution units;
- wherein the first local register file is further configured so that the third and fourth execution units can write to the first plurality of local registers, the third execution unit can read from the first plurality of local registers, and the fourth execution unit cannot read from the first plurality of local registers;
- and
- wherein the second local register file is further configured so that the third and fourth execution units can write to the second plurality of local registers, the fourth execution unit can read from the second plurality of local registers, and the third execution unit cannot read from the second plurality of local registers.
8 more elements
A semiconductor device comprising:
- a first execution unit;
- a second execution unit;
- a first local register file including a first plurality of local registers, wherein the first local register file is coupled to the first and second execution units and configured so that the first and second execution units can write to the first plurality of local registers, the first execution unit can read from the first plurality of local registers, and the second execution unit cannot read from the first plurality of local registers;
- a second local register file including a second plurality of local registers, wherein the second local register file is coupled to the first and second execution units and configured so that the first and second execution units can write to the second plurality of local registers, the second execution unit can read from the second plurality of local registers, and the first execution unit cannot read from the second plurality of local registers;
- a third execution unit;
- and
- a third local register file including a third plurality of local registers, wherein the third local register file is coupled to the first, second, and third execution units and configured so that each of the first, second, and third execution units can write to the third plurality of local registers, the third execution unit can read from the third plurality of local registers, and the first and second execution units cannot read from the third plurality of local registers;
- wherein the third plurality of local registers each have a first size that is different than a size of the first plurality of local registers and the second plurality of local registers;
- and
- wherein the third local register file is further configured so that, when either the first execution unit or the second execution unit writes a value having a size that is greater than the first size to a local register of the third plurality of local registers, bits of the value that exceed the first size are discarded.
7 more elements
Dependencies are inferred from the claim text.