Addition instructions with independent carry chains
AssigneeIntel Corporation
InventorsVinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk, Martin G. Dixon, Sean P. Mirkes, Matthew C. Merten, Tong Li, Bret T. Toll, I
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Abstract
A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.
Claims16
A method performed by a processor comprising a multi-bit flags register having a plurality of arithmetic flag bits, the method comprising:
- fetching, using instruction fetch circuitry, first and second addition instructions;
- decoding, using decode circuitry, the first and second addition instructions, wherein the first and second addition instructions have opcodes specifying, respectively, different first and second flag bits, of the plurality of arithmetic flag bits, from which to read a respective carry-in of the first and second addition instructions and to which to write a respective carry-out of the first and second addition instructions;
- and
- executing, using execution circuitry, the first and second addition instructions in parallel, writing carry-outs to the first and second flag bits, without writing to other flag bits.
A processor comprising:
- a multi-bit flags register having a plurality of arithmetic flag bits;
- fetch circuitry to fetch first and second addition instructions;
- decode circuitry to decode the first and second addition instructions, wherein the first and second addition instructions have opcodes specifying, respectively, different first and second flag bits, of the plurality of arithmetic flag bits, from which to read a respective carry-in of the first and second addition instructions and to which to write a respective carry-out of the first and second addition instructions;
- and
- execution circuitry to execute the first and second addition instructions in parallel, writing carry-outs to the first and second flag bits, without writing to other flag bits.
A non-transitory machine-readable medium containing code, that when executed, causes a processor comprising a multi-bit flags register having a plurality of arithmetic flag bits to perform operations comprising:
- fetching, using instruction fetch circuitry, first and second addition instructions;
- decoding, using decode circuitry, the first and second addition instructions, wherein the first and second addition instructions have opcodes specifying, respectively, different first and second flag bits, of the plurality of arithmetic flag bits, from which to read a respective carry-in of the first and second addition instructions and to which to write a respective carry-out of the first and second addition instructions;
- and
- executing, using execution circuitry, the first and second addition instructions in parallel, writing carry-outs-to the first and second flag bits, without writing to other flag bits.
Dependencies are inferred from the claim text.