Method and apparatus for performing synthesis for field programmable gate array embedded feature placement

A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method for designing and configuring a system on a field programmable gate array (FPGA), comprising:

• identifying a first portion of the system that is implemented greater than a predetermined number of times;
• generating a structural netlist that describes how to implement the first portion a plurality of times on the FPGA and that leverages a repetitive nature of implementing the portion;
• identifying a second portion of the system that is implemented greater than the predetermined number of times;
• and
• generating another structural netlist that describes how to implement the second portion of the system a plurality of times on the FPGA and that leverages a repetitive nature of implementing the second portion, wherein the identifying and generating is performed prior to synthesizing and placing other portions of the system that are not implemented greater than the predetermined number of time.

A system designer for designing and configuring a system on a field programmable gate array (FPGA), comprising:

• a synthesis for embedded feature placement (SEFP) unit that identifies a portion of the system that is implemented greater than a predetermined number of times, and that generates a structural netlist that describes how to implement the portion of the system a plurality of times on the FPGA by leveraging a repetitive nature of implementing the portion, wherein the identifying and generating is performed prior to synthesizing and placing other portions of the system that are not implemented greater than the predetermined number of time;
• a synthesis unit that synthesizes other portions of the system on the FPGA with the portion of the system in accordance with the structural netlist;
• a placement unit that places the other portions of the system with the portion of the system on the FPGA in accordance with the structural netlist;
• and
• an assembly unit that configures the FPGA with a configuration file that includes a design for the system that reflects the synthesizing and placing, wherein the configuring physically transforms resources on the FPGA to implement the system.