Host-based bit string conversion

A method, comprising:

• receiving, by a conversion component memory resource resident on a host computing system, data stored in a memory array of a memory device coupled to the host computing system and comprising a bit string having a first format that supports arithmetic operations to a first level of precision;
• performing, by a processing device coupled to the conversion component memory resource, an operation to convert the bit string to yield a converted bit string having a second format that supports arithmetic operations to a second level of precision that is different from the first level of precision;
• transferring the converted bit string to acceleration circuitry comprising logic circuitry and a non-volatile memory resource, the acceleration circuitry resident on the memory device coupled to the host computing system;
• performing, using the acceleration circuitry and as part of performance of a machine learning operation, an arithmetic operation or a logical operation, or both, using the converted bit string in the absence of an intervening command from the host computing device;
• and
• writing a result of the arithmetic operation or the logical operation, or both to at least one of the memory array or the host computing system.

A system, comprising:

• a host computing system comprising a conversion component memory resource and a processing device;
• and
• a non-volatile memory device comprising acceleration circuitry and a memory array, wherein the non-volatile memory device is coupled to the host computing system, and wherein the acceleration circuitry comprises logic circuitry and a memory resource, and wherein:
• the conversion component memory resource is configured to receive a bit string having a first format that supports arithmetic operations to a first level of precision from the memory array;
• the processing device is configured to:
• convert the bit string to yield a converted bit string having a second format that supports arithmetic operations to a second level of precision;
• cause the converted bit string to be transferred to the memory resource of the acceleration circuitry;
• and
• the acceleration circuitry is configured to:
• store the converted bit string in the memory resource of the acceleration circuitry;
• cause, within the acceleration circuitry, performance of an arithmetic operation or a logical operation, or both, using the converted bit string responsive to receipt of the converted bit string in the absence of an intervening command generated by the host computing system.