US 11,079,964 B2 · Memory system

Abstract

A memory system may include a semiconductor memory and a memory controller. The memory controller may include an adjustment circuit configured to receive a first signal having a first duty cycle, and intermittently output a second signal to an outside of the memory controller on the basis of a control signal, the second signal having a second duty cycle which is different from the first duty cycle. The memory controller may further include a selector circuit configured to receive the second signal, receive a third signal which is generated on the basis of the second signal, and output a selected one of the second signal and the third signal. The memory controller may further include a control circuit configured to generate the control signal on the basis of the selected one of the second signal and the third signal output from the selector circuit.

Claims20

Dependent claims

A memory system comprising:

a semiconductor memory;
and
a memory controller including:
an adjustment circuit configured to receive a first signal having a first duty cycle, generate a second signal on the basis of the first signal and a control signal, the second signal having a second duty cycle which is different from the first duty cycle, and intermittently output the second signal to an outside of the memory controller;
a selector circuit configured to receive a third signal and a fourth signal which are generated on the basis of the second signal, and output a detection target signal on the basis of a selected one of the third signal and the fourth signal;
and
a control circuit configured to generate the control signal on the basis of the detection target signal.

4 more elements

Dependencies are inferred from the claim text.

Memory system

Life of this patent

Memory system

Life of this patent

Abstract

Claims20