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US 11,079,946 B2Granted
Write training in memory devices
AssigneeMicron Technology, Inc.
InventorsLuigi Pilolli, Ali Feiz Zarrin Ghalam, Guan Wang, Qiang Tang
Life of this patent
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Abstract
A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.
Claims19
A memory die comprising:
- a plurality of input/output (I/O) nodes to receive a periodic predefined data pattern;
- a data strobe node to receive a data strobe signal;
- a delay circuit coupled to the I/O nodes to delay the data received on each I/O node based on a trim value for each I/O node;
- a latch coupled to the delay circuit to latch the delayed data for each I/O node in response to the data strobe signal;
- a cache register to store the latched data;
- a state machine to change the trim value for each I/O node after each period of the predefined data pattern is received;
- and
- a controller to select the trim value for each I/O node based on a comparison between the stored data and an expected data pattern for each I/O node;
- wherein the controller is to generate a table indicating which stored data for each I/O node for each period of the predefined data pattern matches the expected data pattern for each I/O node and which stored data for each I/O node for each period of the predefined data pattern does not match the expected data pattern for each I/O node, and
- wherein the controller selects the trim value for each I/O node based on the table.
7 more elements
A memory system comprising:
- a host to provide a periodic predefined data pattern and a data strobe signal;
- and
- a first memory die coupled to the host, the first memory die comprising:
- a plurality of input/output (I/O) nodes to receive the periodic predefined data pattern;
- a data strobe node to receive the data strobe signal;
- a delay circuit to adjust a delay of data received by each I/O node based on a trim value for each I/O node and to adjust a delay of the data strobe signal based on a trim value for the data strobe node;
- a latch to latch the data received by each I/O node in response to the data strobe signal;
- and
- a controller to compare the latched data to an expected data pattern and to set the trim value for each I/O node and the trim value for the data strobe signal based on the comparison;
- wherein the controller is to compare the latched data to the expected data pattern to generate a table indicating which latched data matches the expected data pattern and which latched data does not match the expected data pattern, and
- wherein the controller sets the trim value for each I/O node based on the table.
8 more elements
A method for write training in a memory system, the method comprising:
- loading, via a host, a periodic predefined data pattern to a plurality of input/output (I/O) nodes of a first memory die;
- changing, within the first memory die, a trim value of a delay for each I/O node of the first memory die after each period of the predefined data pattern;
- latching, within the first memory die, the delayed data for each I/O node of the first memory die;
- comparing, within the first memory die, the latched data for each I/O node of the first memory die to an expected data pattern;
- setting, within the first memory die, the trim value of the delay for each I/O node of the first memory die based on the comparison;
- and
- generating a table indicating which latched data for each I/O node of the first memory die matches the expected data pattern and which latched data for each I/O node of the first memory die does not match the expected data pattern;
- wherein setting the trim value of the delay for each I/O node of the first memory die comprises setting the trim value of the delay for each I/O node of the first memory die based on the table.
5 more elements
Dependencies are inferred from the claim text.