3-D stacked memory with reconfigurable compute logic
AssigneeSamsung Electronics Co., Ltd.
InventorsMu-Tien Chang, Prasun Gera, Dimin Niu, Hongzhong Zheng
Life of this patent
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Abstract
A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.
Claims21
A 3D-stacked (3DS) memory device comprising:
- a base die comprising a plurality of switches configured to direct data flow, and a plurality of arithmetic logic units (ALUs) configured to compute data;
- a plurality of memory dies stacked on the base die;
- and
- an interface configured to transfer signals to control the base die, and comprising:
- a control bus configured to transmit commands from a host to the base die, the commands comprising a mode register set command (MRS command) to configure the 3DS memory device to operate in a processor in memory (PIM) mode to compute the data by interpreting traditional commands comprising one or more DRAM access commands comprising a “read” command, an “activate” command, a “precharge” command, or a “refresh” command to perform a memory access operation as respective logic commands comprising one or more of an “add” command, a “multiply” command, a “divide” command, a “compare” command, a “shift” command, an “and” command, an “or” command, or an “xor” command;
- and
- a data bus configured to transmit data between the host and the base die, wherein the base die is configured to:
- receive, from the host, a traditional command of the traditional commands;
- and
- translate the traditional command into a respective one of the logic commands to perform an arithmetic operation on the data via the ALUs.
A method of operating a 3D-stacked (3DS) memory device comprising a base die comprising a plurality of switches and a plurality of arithmetic logic units (ALUs), a plurality of memory dies stacked on the base die, and an interface configured to control the base die and comprising a control bus configured to transmit commands from a host to the base die, the commands comprising a mode register set command (MRS command) to configure the 3DS memory device to operate in a processor in memory (PIM) mode to compute data by interpreting traditional commands comprising one or more DRAM access commands comprising a “read” command, an “activate” command, a “precharge” command, or a “refresh” command as respective logic commands comprising one or more of an “add” command, a “multiply” command, a “divide” command, a “compare” command, a “shift” command, an “and” command, an “or” command, or an “xor” command, and a data bus configured to transmit data between the host and the base die, the method comprising:
- configuring the switches to direct data flow according to configuration instructions;
- controlling operations of the ALUs to compute data according to the logic commands;
- and
- storing the computed data in the memory dies,
- wherein the base die is configured to receive, from the host, the traditional commands to perform memory access operations, or to translate the traditional commands into the logic commands to perform arithmetic operations on the data via the ALUs.
An interface of a memory device comprising a processor in memory, the interface comprising:
- a control bus configured to transfer commands from an external host to the memory device, the commands comprising a mode register set command (MRS command) to configure the memory device to operate in a processor in memory (PIM) mode to compute data by interpreting traditional commands comprising one or more DRAM access commands comprising a “read” command, an “activate” command, a “precharge” command, or a “refresh” command as logic commands comprising one or more of an “add” command, a “multiply” command, a “divide” command, a “compare” command, a “shift” command, an “and” command, an “or” command, or an “xor” command;
- and
- a data bus configured to transfer data between the memory device and the host,
- wherein the interface is configured to transfer the commands to set the memory device to operate in a PIM mode to compute the data, and to set the memory device to operate in a normal mode to perform memory functions, and
- wherein the memory device is configured to:
- translate the traditional memory commands received from the host into the logic commands to compute the data according to the logic commands when in the PIM mode;
- and to
- perform the memory functions according to the traditional memory commands when in the normal mode.
Dependencies are inferred from the claim text.