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US 11,079,830 B2Granted
Apparatus and method for reducing di/dt
AssigneeIntel Corporation
InventorsJaydeep P. Kulkarni, Yong Shim, Pascal A. Meinerzhagen
Life of this patent
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Abstract
Described is an apparatus which comprises: a controllable power gate coupled to an ungated power supply node and a gated power supply node; and a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node.
Claims26
An apparatus comprising:
- a controllable power gate coupled to an ungated power supply node and a gated power supply node;
- a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge-pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node, wherein the charge-pump circuit has substantially constant charge transfer efficiency;
- and
- a transistor controllable by a low power mode signal, wherein the transistor is coupled in series with the charge-pump circuit such that the transistor and the charge-pump circuit together are coupled in parallel to the controllable power gate.
1 more element
An apparatus comprising:
- an ungated power supply node;
- a gated power supply node;
- a primary power gate coupled to the ungated power supply node and the gated power supply node;
- a secondary power gate coupled to the ungated power supply node and the gated power supply node, the secondary power gate being smaller in size than the primary power gate, wherein the primary power gate and the secondary power gate have a same conductivity type;
- logic to generate a pulse;
- and
- a charge-pump circuit operable to be turned on and off according to the pulse, wherein the charge-pump circuit is coupled in parallel to a controllable power gate and also coupled to the ungated power supply node and the gated power supply node, and wherein the charge-pump circuit has substantially constant charge transfer efficiency.
4 more elements
A system comprising:
- a memory;
- a processor coupled to the memory, the processor including:
- a controllable power gate coupled to an ungated power supply node and a gated power supply node;
- a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node, wherein the charge-pump circuit has substantially constant charge transfer efficiency;
- and
- a transistor controllable by a low power mode signal, wherein the transistor is coupled in series with the charge-pump circuit such that the transistor and the charge-pump circuit together are coupled in parallel to the controllable power gate;
- and
- a wireless interface to allow the processor to communicate with another device.
5 more elements
An apparatus comprising:
- a controllable power gate coupled to an ungated power supply node and a gated power supply node;
- a charge-pump coupled to the controllable power gate;
- a logic to turn on the charge pump when the controllable power gate is just turned on, and to turn off the charge pump during a voltage droop on the gated power supply node;
- and
- a transistor controllable by a low power mode signal, wherein the transistor is coupled in series with the charge-pump such that the transistor and the charge-pump together are coupled in parallel to the controllable power gate.
2 more elements
Dependencies are inferred from the claim text.