Integrated power and thermal management in non-volatile memory
AssigneeWestern Digital Technologies, Inc.
InventorsMark Hatch, Reed Tidwell, David Wagner, Mark Hardiman
Life of this patent
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Abstract
A non-volatile storage device comprises non-volatile memory cells, clocked circuity, and one or more control circuits. The one or more control circuits are configured to process commands to access the non-volatile memory cells using the clocked circuity, implement a power control loop to regulate power consumption of the non-volatile storage device based on a first feedback signal, implement a temperature control loop to regulate temperature of the non-volatile storage device based on a second feedback signal, and implement a clock frequency control loop to regulate one or more clock frequencies of the clocked circuitry based on a third feedback signal.
Claims19
A non-volatile storage device, comprising:
- non-volatile memory cells;
- clocked circuitry;
- and
- one or more control circuits configured to:
- process commands to access the non-volatile memory cells using the clocked circuitry;
- implement a power control loop to regulate power consumption of the non-volatile storage device based on a first feedback signal, the power control loop having a first update rate;
- implement a clock frequency control loop to regulate one or more clock frequencies of the clocked circuitry based on a second feedback signal, the clock frequency control loop having a second update rate that is slower than the first update rate;
- and
- implement a temperature control loop to regulate temperature of the non-volatile storage device based on a third feedback signal, the temperature control loop having a third update rate that is slower than the second update rate.
A method of operating a non-volatile storage device comprising non-volatile memory cells, the method comprising:
- operating one or more processors to execute commands to access the non-volatile memory cells;
- regulating power usage in the non-volatile storage device based on a target power level while operating the one or more processors, including issuing power credits to execute the commands;
- limiting operating temperature of the non-volatile storage device to below a threshold temperature, including establishing the target power level;
- and
- reducing a frequency of one or more clock signals of the one or more processors in response to an increase of backlog of the commands.
A non-volatile storage device, comprising:
- non-volatile memory cells;
- and
- a non-volatile memory controller comprising one or more processors, the non-volatile memory controller comprising:
- means for processing commands to access the non-volatile memory cells;
- means for controlling power usage of the non-volatile storage device using a first closed control loop having a first bandwidth;
- means for controlling operating frequencies of the one or more processors using a second closed control loop having a second bandwidth that is less than the first bandwidth;
- and
- means for controlling operating temperature of the non-volatile storage device using a third closed control loop having a third bandwidth that is less than the second bandwidth.
Dependencies are inferred from the claim text.