# US 11,079,784 B2 · Power management integrated circuit (PMIC), memory module and computing system including a PMIC, and method of operating a memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,079,784 B2 - Document ID: US11079784B2 - Status: Granted - Kind: B2 - Application number: 16/801,221 - Filed: 2020-02-26 - Published: 2020-10-22 - Granted: 2021-08-03 - Earliest claimed: 2019-04-19 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jinseong Yun; Kyudong Lee; Jaejun Lee - Web page: https://patentgrep.com/patent/US11079784B2 ## CPC - G05F 1/575: characterised by the feedback circuit - G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G11C 2029/0409: {Online test} - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A power management integrated circuit (PMIC) includes a voltage regulator, a monitoring circuit, and a count register. The voltage regulator is configured to generate an output voltage. The monitoring circuit is configured to receive a feedback voltage of the output voltage, and to determine at each of periodic intervals whether the feedback voltage is outside a threshold voltage range. The count register is configured to store a count value indicative of a number of times the feedback voltage is determined by the monitoring circuit to be outside the threshold voltage range. ## Claims ### Claim 1 A power management integrated circuit (PMIC), comprising: a voltage regulator configured to generate an output voltage, and to regulate the output voltage using a feedback voltage of the output voltage; a monitoring circuit configured to receive the feedback voltage, and to determine at each of periodic intervals whether the feedback voltage is outside a threshold voltage range; and a count register configured to store a count value indicative of a number of times the feedback voltage is determined by the monitoring circuit to be outside the threshold voltage range. ### Claim 2 (depends on 1) The PMIC of claim 1, further comprising an interface (I/F) circuit configured to output monitoring data indicative of the count value stored in the count register to an external device. ### Claim 3 (depends on 2) The PMIC of claim 2, further comprising a setting register, wherein the I/F circuit is further configured to receive operational parameters controlling an operation of the monitoring circuit and to store the operational parameters in the setting register. ### Claim 4 (depends on 3) The PMIC of claim 3, wherein the operational parameters include at least one of the threshold voltage range, a duration of each of the periodic intervals, a monitoring time during which the monitoring circuit is operative, a deviation from a target feedback voltage which defines the threshold voltage range, a monitoring start trigger to start monitoring by the monitoring circuit, and a monitoring stop trigger to stop monitoring by the monitoring circuit. ### Claim 5 (depends on 3) The PMIC of claim 3, further comprising a data pin terminal coupled to the I/F circuit, wherein the operational parameters are received at the data pin terminal. ### Claim 6 (depends on 1) The PMIC of claim 1, wherein the monitoring circuit comprises: a first comparator configured to compare the feedback voltage with an upper threshold voltage of the threshold voltage range at each of the periodic intervals; a first counter configured to increment a first count value at each of the periodic intervals in which the first comparator indicates that the feedback voltage is more than the upper threshold voltage; a second comparator configured to compare the feedback voltage with a lower threshold voltage of the threshold voltage range at each of the periodic intervals; and a second counter configured to increment a second count value at each of the periodic intervals in which the second comparator indicates that the feedback voltage is less than the lower threshold voltage. ### Claim 7 (depends on 6) The PMIC of claim 6, wherein the count register is configured to store the first count value of the first counter, and the second count value of the second counter. ### Claim 8 (depends on 7) The PMIC of claim 7, wherein the count register is further configured to store a third count value corresponding to a sum of the first and second count values. ### Claim 9 (depends on 7) The PMIC of claim 7, further comprising an interface (I/F) circuit configured to output monitoring data corresponding to at least one of the first and second count values to an external device. ### Claim 10 (depends on 1) The PMIC of claim 1, the voltage regulator comprising: a voltage generator configured to output a reference voltage; a comparator configured to compare the reference voltage with the feedback voltage; and a voltage driver configured to generate the output voltage based on an output of the comparator. ### Claim 11 (depends on 10) The PMIC of claim 10, further comprising a feedback voltage pin terminal connected to the comparator and the monitoring circuit. ### Claim 12 (depends on 1) The PMIC of claim 1, wherein the voltage regulator is a first voltage regulator, the output voltage is a first output voltage, the monitoring circuit is a first monitoring circuit, the count register is a first count register, the count value is a first count value, the threshold voltage range is a first threshold voltage range, and the feedback voltage is a first feedback voltage, and wherein the PMIC further comprises: a second voltage regulator configured to generate a second output voltage; a second monitoring circuit configured to receive a second feedback voltage of the second output voltage, and to determine at each of periodic intervals whether the second feedback voltage is outside a second threshold voltage range; and a second count register configured to store a second count value indicative of a number of times the second feedback voltage is determined by the second monitoring circuit to be outside the second voltage range. ### Claim 13 (depends on 1) The PMIC of claim 1, wherein the voltage regulator is a first voltage regulator, the output voltage is a first output voltage, and the feedback voltage is a first feedback voltage, and wherein the PMIC further comprising: a second voltage regulator configured to generate a second output voltage; and a multiplexer circuit configured to selectively apply one of the first feedback voltage and a second feedback voltage of the second output voltage to the monitoring circuit, wherein the monitoring circuit is configured to store a second count value in the count register indicative of a number of times the second feedback voltage is determined to be outside a second voltage range. ### Claim 14 (depends on 1) The PMIC of claim 1, wherein the feedback voltage is obtained by voltage dividing the output voltage. ### Claim 15 A dynamic random access memory (DRAM) module, comprising: a module board; a DRAM device mounted to the module board, the DRAM device including a plurality of operating voltage terminals; and a power management integrated circuit (PMIC) mounted to the module board, the PMIC including a plurality of voltage regulators configured to generate a plurality of operating voltages applied to the respective plurality of operating voltage terminals of the DRAM, the PMIC configured to receive a plurality of feedback voltages of the respective plurality of operating voltages, wherein the voltage regulators are further configured to regulate the respective plurality of operating voltages using the feedback voltages, wherein the PMIC includes a monitoring circuit configured to determine a number of times each of the plurality of feedback voltages is outside a respective threshold voltage range, and to store the number of times in a count register. ### Claim 16 (depends on 15) The DRAM module of claim 15, further comprising: at least one first pin terminal; and a serial presence detect (SPD) circuit mounted to the module board and configured exchange PMIC control and data signals between the at least one first pin terminal and the PMIC. ### Claim 17 (depends on 16) The DRAM module of claim 16, further comprising: at least one second pin terminal; and a data buffer circuit mounted on the module board and configured to exchange memory data signals between the at least one second terminal and the DRAM device. ### Claim 18 (depends on 17) The DRAM module of claim 17, further comprising: at least one third pin terminal; and a register clock driver circuit mounted on the module board and configured to exchange command and address signals between the at least one third pin terminal and the DRAM device. ### Claim 19 (depends on 18) The DRAM module of claim 18, further comprising at least one fourth pin terminal for supplying an input voltage to the PMIC.