# US 11,079,782 B2 · Low power ideal diode control circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,079,782 B2 - Document ID: US11079782B2 - Status: Granted - Kind: B2 - Application number: 16/678,733 - Filed: 2019-11-08 - Published: 2020-03-05 - Granted: 2021-08-03 - Earliest claimed: 2014-12-24 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Timothy Bryan Merkin; Hassan Pooya Forghani-Zadeh - Web page: https://patentgrep.com/patent/US11079782B2 ## CPC - G05F 1/575: characterised by the feedback circuit - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract In described examples of a circuit that operates as a low-power ideal diode, and an IC chip that contains the ideal diode circuit, the circuit includes: a first P-channel transistor connected to receive an input voltage on a first terminal and to provide an output voltage on a second terminal; a first amplifier connected to receive the input voltage and the output voltage and to provide a first signal that dynamically biases a gate of the first P-channel transistor as a function of the voltage across the first P-channel transistor; and a second amplifier connected to receive the input voltage and the output voltage and to provide a second signal that acts to turn off the gate of the first P-channel transistor responsive to the input voltage being less than the output voltage. ## Claims ### Claim 1 An apparatus comprising: a pass transistor having a first current terminal coupled to a voltage input terminal, a second current terminal coupled to a voltage output terminal, and a gate terminal; an amplifier having a first input coupled to the voltage input terminal, and a second input coupled to the voltage output terminal, the amplifier configured to generate a turn-off signal when the voltage output terminal has a greater voltage than the voltage input terminal; and an output stage having: a p-channel field-effect transistor (PFET) having a source coupled to the gate of the pass transistor, a gate configured to receive the turn-off signal, and a drain coupled to a ground terminal; an n-channel field-effect transistor (NFET) having a drain coupled to the gate of the PFET, a gate, and a source coupled to the ground terminal; and a resistor coupled between the voltage output terminal and the gate of the PFET. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the pass transistor includes a second PFET, and the gate of the pass transistor is coupled to a body of the pass transistor. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the output stage includes a second resistor coupled between the gate of the pass transistor and the voltage output terminal. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the amplifier includes: a second PFET having a source coupled to the voltage input terminal, a gate, and a drain coupled to the gate of the second PFET; and a third PFET having a source coupled to the voltage output terminal, a gate coupled to the gate of the second PFET, and a drain coupled to the gate of the PFET. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the amplifier includes: a second PFET having a source coupled to the voltage input terminal, a gate, and a drain coupled to the gate of the second PFET; and a third PFET having a source coupled to the voltage output terminal, a gate coupled to the gate of the second PFET, and a drain coupled to the source of the PFET. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the amplifier includes: a second PFET having a source coupled to the voltage input terminal, a gate, and a drain coupled to the gate of the second PFET; a third PFET having a source coupled to the voltage output terminal, a gate coupled to the gate of the second PFET, and a drain coupled to the gate of the PFET; and a fourth PFET having a source coupled to the voltage output terminal, a gate coupled to the gate of the third PFET, and a drain coupled to the source of the PFET. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the amplifier includes a current source coupled between the drain of the third PFET and the ground terminal. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the gate of the NFET is configured to receive a bias signal representing a voltage difference of the voltage input terminal above the voltage output terminal. ### Claim 9 (depends on 1) The apparatus of claim 1, further comprising: a second amplifier having a first input coupled to the voltage input terminal, and a second input coupled to the voltage output terminal, the second amplifier configured to generate a bias signal based on a voltage difference of the voltage input terminal above the voltage output terminal. ### Claim 10 (depends on 1) The apparatus of claim 1, further comprising: a second amplifier including: a second PFET having a source coupled to the voltage output terminal, a gate, and a drain coupled to the gate of the second PFET; a third PFET having a source coupled to the voltage input terminal, a gate coupled to the gate of the second PFET, and a drain; and a current mirror configured to mirror a first current from the drain of the third PFET to the drain of the NFET. ### Claim 11 An apparatus comprising: a pass transistor having a first current terminal coupled to a voltage input terminal, a second current terminal coupled to a voltage output terminal, and a gate terminal; an amplifier having: a first PFET having a source coupled to the voltage input terminal, a gate, and a drain coupled to the gate of the second PFET; and a second PFET having a source coupled to the voltage output terminal, a gate coupled to the gate of the first PFET, and a drain configured to deliver a turn-off signal; and an output stage configured to regulate the gate of the pass transistor based on a bias signal representing a voltage difference of the voltage input terminal and the voltage output terminal, and configured to turn off the gate of the pass transistor based on the turn-off signal. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the pass transistor includes a third PFET, and the gate of the pass transistor is coupled to a body of the pass transistor. ### Claim 13 (depends on 11) The apparatus of claim 11, wherein the output stage includes: a third PFET having a source coupled to the gate of the pass transistor, a gate configured to receive the turn-off signal from the drain of the second PFET, and a drain coupled to a ground terminal; an NFET having a drain coupled to the gate of the third PFET, a gate configured to receive the bias signal, and a source coupled to the ground terminal; and a resistor coupled between the voltage output terminal and the gate of the third PFET. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the output stage includes a second resistor coupled between the gate of the pass transistor and the voltage output terminal. ### Claim 15 (depends on 13) The apparatus of claim 13, wherein the amplifier includes a fourth PFET having a source coupled to the voltage output terminal, a gate coupled to the gate of the second PFET, and a drain coupled to the source of the third PFET. ### Claim 16 (depends on 11) The apparatus of claim 11, further comprising: a second amplifier having a first input coupled to the voltage input terminal, and a second input coupled to the voltage output terminal, the second amplifier configured to generate the bias signal. ### Claim 17 (depends on 11) The apparatus of claim 11, further comprising: a second amplifier including: a third PFET having a source coupled to the voltage output terminal, a gate, and a drain coupled to the gate of the third PFET; a fourth PFET having a source coupled to the voltage input terminal, a gate coupled to the gate of the third PFET, and a drain; and a second NFET having a drain coupled to the drain of the fourth PFET, a gate coupled to the drain of the second NFET and configured to deliver the bias signal, and a source coupled to a ground terminal. ### Claim 18 An apparatus comprising: a pass transistor having a first current terminal coupled to a voltage input terminal, a second current terminal coupled to a voltage output terminal, and a gate terminal; an amplifier having: a first PFET having a source coupled to the voltage input terminal, a gate, and a drain coupled to the gate of the second PFET; and a second PFET having a source coupled to the voltage output terminal, a gate coupled to the gate of the first PFET, and a drain; and an output stage configured to regulate the gate of the pass transistor based on a bias signal representing a voltage difference of the voltage input terminal and the voltage output terminal, the output stage including: a third PFET having a source coupled to the gate of the pass transistor, a gate coupled to the drain of the second PFET, and a drain coupled to a ground terminal; an NFET having a drain coupled to the gate of the third PFET, a gate, and a source coupled to the ground terminal; and a resistor having coupled between the voltage output terminal and the gate of the third PFET. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the output stage includes a second resistor coupled between the gate of the pass transistor and the voltage output terminal. ### Claim 20 (depends on 18) The apparatus of claim 18, wherein the amplifier includes a fourth PFET having a source coupled to the voltage output terminal, a gate coupled to the gate of the second PFET, and a drain coupled to the source of the third PFET.