# US 11,079,780 B2 · Supply voltage regulator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,079,780 B2 - Document ID: US11079780B2 - Status: Granted - Kind: B2 - Application number: 16/677,284 - Filed: 2019-11-07 - Published: 2020-03-05 - Granted: 2021-08-03 - Earliest claimed: 2018-07-12 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Jayateerth Pandurang Mathad; Rajat Chauhan - Web page: https://patentgrep.com/patent/US11079780B2 ## CPC - G05F 1/571: with overvoltage detector - G05F 1/59: including plural semiconductor devices as final control devices for a single load - G05F 3/24: wherein the transistors are of the field-effect type only (G05F3/205, G05F3/26, G05F3/30 take precedence) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit. ## Claims ### Claim 1 A circuit comprising: a control sub-circuit comprising: a first transistor having a first gate, a first drain, and a first source; a second transistor having a second gate, a second drain, and a second source, the second gate coupled to the first source; a third transistor having a third gate, a third drain, and a third source; and a fourth transistor having a fourth gate, a fourth drain, and a fourth source, the fourth gate coupled to the third drain, the fourth source coupled to the third source, and the fourth drain coupled to the second source; and a fast turn-off sub-circuit coupled to the fourth drain. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the fast turn-off sub-circuit is configured to couple the fourth gate to a voltage supply to bypass a bias current turn off of the fourth transistor and rapidly turn off the fourth transistor when an output voltage at the fourth drain exceeds a clamp voltage of the fast turn-off sub-circuit. ### Claim 3 (depends on 1) The circuit of claim 1, further comprising: a fast turn-on sub-circuit coupled to the third gate, and the fast turn-on sub-circuit configured to turn on the first transistor, the second transistor, the third transistor, or the fourth transistor more rapidly than in the absence of the fast turn-on sub-circuit. ### Claim 4 (depends on 3) The circuit of claim 3, wherein the fast turn-on sub-circuit is configured to couple the fourth gate to a ground voltage to rapidly turn on the fourth transistor for a period of time to bypass a bias current turn on of the fourth transistor to rapidly turn on the fourth transistor. ### Claim 5 (depends on 1) The circuit of claim 1, further comprising: a voltage protection sub-circuit configured to protect the control sub-circuit from a voltage input signal that exceeds a tolerance of the control sub-circuit. ### Claim 6 (depends on 1) The circuit of claim 1, further comprising: a node initialization sub-circuit coupled to the first gate, and the node initialization sub-circuit configured to initialize nodes of the circuit. ### Claim 7 (depends on 6) The circuit of claim 6, wherein the control sub-circuit is configured to couple to bias current sources, and wherein the node initialization sub-circuit is configured to initialize the nodes of the control sub-circuit during a start-up period of the bias current sources. ### Claim 8 (depends on 1) The circuit of claim 1, further comprising: a diode stack coupled to the first gate. ### Claim 9 (depends on 8) The circuit of claim 8, further comprising: a fifth transistor having a fifth gate, a fifth source, and a fifth drain, the fifth gate coupled to the diode stack. ### Claim 10 (depends on 9) The circuit of claim 9, further comprising: a sixth transistor having a sixth gate, a sixth source, and a sixth drain, the sixth gate coupled to the fifth drain and the sixth source coupled to the third gate. ### Claim 11 A circuit comprising: a control sub-circuit comprising: a first transistor having a first gate, a first drain, and a first source; a second transistor having a second gate, a second drain, and a second source, the second gate coupled to the first source; a third transistor having a third gate, a third drain, and a third source; and a fourth transistor having a fourth gate, a fourth drain, and a fourth source, the fourth gate coupled to the third drain, the fourth drain coupled to the second source, and the fourth source coupled to the third source; and a fast turn-on sub-circuit coupled to the third gate. ### Claim 12 (depends on 11) The circuit of claim 11, wherein the fast turn-on sub-circuit is configured to couple the fourth gate to a ground voltage to rapidly turn on the fourth transistor for a period of time to bypass a bias current turn on of the fourth transistor to rapidly turn on the fourth transistor. ### Claim 13 (depends on 11) The circuit of claim 11, further comprising: a fast turn-off sub-circuit coupled to the fourth drain, and the fast turn-off sub-circuit configured to turn off the first transistor, the second transistor, the third transistor, or the fourth transistor more rapidly than in the absence of the fast turn-off sub-circuit. ### Claim 14 (depends on 13) The circuit of claim 13, wherein the fast turn-off sub-circuit is configured to couple the fourth gate to a voltage supply to bypass a bias current turn off of the fourth transistor and rapidly turn off the fourth transistor when an output voltage present at the fourth drain exceeds a clamp voltage of the fast turn-off sub-circuit. ### Claim 15 (depends on 11) The circuit of claim 11, further comprising: a voltage protection sub-circuit configured to protect the control sub-circuit from a voltage input signal that exceeds a tolerance of the control sub-circuit. ### Claim 16 (depends on 11) The circuit of claim 11, further comprising: a node initialization sub-circuit coupled to the first gate, and the node initialization sub-circuit configured to initialize nodes of the circuit. ### Claim 17 (depends on 16) The circuit of claim 16, wherein the control sub-circuit is configured to couple to bias current sources, and wherein the node initialization sub-circuit is configured to initialize the nodes of the control sub-circuit during a start-up period of the bias current sources. ### Claim 18 (depends on 11) The circuit of claim 11, further comprising: a diode stack coupled to the first gate. ### Claim 19 (depends on 18) The circuit of claim 18, further comprising: a fifth transistor having a fifth gate, a fifth drain, and a fifth source, the fifth gate coupled to the diode stack, and a source terminal. ### Claim 20 (depends on 19) The circuit of claim 19, further comprising: a sixth transistor having a sixth gate, a sixth drain, and a sixth source, the sixth drain coupled to the fifth drain and the sixth source coupled to the third gate. ### Claim 21 A circuit comprising: a control sub-circuit comprising: a first transistor having a first gate, a first drain, and a first source; a second transistor having a second gate, a second drain, and a second source, the second gate coupled to the first source; a third transistor having a third gate, a third drain, and a third source; and fourth transistor having a fourth gate, a fourth drain, and a fourth source, the fourth gate coupled to the third drain, the fourth drain coupled to the second source, and the fourth source coupled to the third source; a voltage protection sub-circuit coupled to the first gate; a fast turn-off sub-circuit coupled to the fourth drain; a fast turn-on sub-circuit coupled to the third gate and to the fourth gate; and a node initialization sub-circuit coupled to the first gate, to the second gate, to the third drain, to the fourth gate, and to the fast turn-on sub-circuit. ### Claim 22 (depends on 21) The circuit of claim 21, wherein the voltage protection sub-circuit is configured to protect the control sub-circuit from a voltage input signal that exceeds a tolerance of the control sub-circuit. ### Claim 23 (depends on 21) The circuit of claim 21, wherein the fast turn-off sub-circuit is configured to turn off at least a portion of the control sub-circuit more rapidly than in the absence of the fast turn-off sub-circuit. ### Claim 24 (depends on 23) The circuit of claim 23, wherein the fast turn-off sub-circuit is configured to couple the fourth gate to a voltage supply to bypass a bias current turn off of the fourth transistor and rapidly turn off the fourth transistor when an output voltage present at the fourth drain exceeds a clamp voltage of the fast turn-off sub-circuit. ### Claim 25 (depends on 23) The circuit of claim 23, wherein the fast turn-on sub-circuit is configured to turn on at least the portion of the control sub-circuit more rapidly than in the absence of the fast turn-on sub-circuit. ### Claim 26 (depends on 25) The circuit of claim 25, wherein the fast turn-on sub-circuit is configured to couple the fourth gate to a ground voltage potential to rapidly turn on the fourth transistor for a period of time to bypass a bias current turn on of the fourth transistor to rapidly turn on the fourth transistor. ### Claim 27 (depends on 21) The circuit of claim 21, wherein the control sub-circuit is configured to couple to bias current sources, and wherein the node initialization sub-circuit is configured to initialize nodes of the control sub-circuit during a start-up period of the bias current sources. ### Claim 28 (depends on 21) The circuit of claim 21, further comprising: a diode stack coupled to the first gate. ### Claim 29 (depends on 28) The circuit of claim 28, further comprising: a fifth transistor having a fifth gate, a fifth drain, and a fifth source, the fifth gate coupled to the diode stack. ### Claim 30 (depends on 29) The circuit of claim 29, further comprising: a sixth transistor having a sixth gate, a sixth drain, and a sixth source, the sixth drain coupled to the fifth drain and the sixth source coupled to the third gate.