# US 11,079,642 B2 · Display panel and display device

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- Number: US 11,079,642 B2
- Document ID: US11079642B2
- Status: Granted
- Kind: B2
- Application number: 16/982,794
- Filed: 2019-02-26
- Published: 2021-01-07
- Granted: 2021-08-03
- Earliest claimed: 2019-01-30
- Assignees: Hkc Corporation Limited; Chongqing Hkc Optoelectronics Technology Co., Ltd.
- Applicants: Hkc Corporation Limited; Chongqing Hkc Optoelectronics Technology Co., Ltd.
- Inventors: Chihtsung Kang
- Web page: https://patentgrep.com/patent/US11079642B2

## CPC

- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G02F 1/136213: {Storage capacitors associated with the pixel electrode}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G02F 2201/123: pixel
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0465: Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
- G09G 2300/0852: being a dynamic memory with more than one capacitor
- G09G 2320/0219: Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
- G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The present disclosure provides a display panel, which includes a plurality of data lines, a plurality of scan lines, and a plurality of pixels, a main scan electrode and a branch scan electrode of the same scan line are electrically connected, and a pixel electrode partially overlaps the branch scan electrode to form a storage capacitance.

## Claims

### Claim 1

A display panel, wherein the display panel comprises:
a plurality of data lines;
a plurality of scan lines, each of the scan lines comprises a main scan electrode and a branch scan electrode, the main scan electrode and the branch scan electrode of a same scan line are electrically connected, and at least a part of branch scan electrodes extend along an extending direction of a data line and are adjacent to the data line; and
a plurality of pixels, each of the pixels comprises a pixel electrode, the pixel electrode partially overlaps the branch scan electrode to form a storage capacitance;
wherein the pixel electrode partially overlaps the branch scan electrode and the main scan electrode of a post-stage scan line; the pixel further comprises a switching component, the switching component comprises a source electrode, a drain electrode, and a gate electrode, a parasitic capacitance Cgs is formed between the source electrode and the gate electrode; when the display panel is in an operating state, a scan signal on each of the scan lines comprises a high level Vgh, a first low level Vgl1, and a second low level Vgl2, the high level Vgh is higher than the first low level Vgl1, the first low level Vgl1 is higher than the second low level Vgl2, the second low level Vgl2 is located on a falling edge side of the high level Vgh, and a second duration of the second low level Vgl2 is equivalent to a first duration of the high level Vgh, a high level falling edge of the scan signal on a current-stage scan line synchronizes with a high level rising edge of the scan signal on the post-stage scan line; the storage capacitance Cst satisfies Cst=(Vgh−Vgl1)×Cgs/(Vgl1−Vgl2).

### Claim 2 (depends on 1)

The display panel according to claim 1, wherein the pixel electrode partially overlaps the main scan electrode and the branch scan electrode to form the storage capacitance.

### Claim 3 (depends on 2)

The display panel according to claim 2, wherein the pixel electrode partially overlaps two of the branch scan electrodes, and the two branch scan electrodes are respectively defined at two sides of the pixel electrode.

### Claim 4

A display panel, wherein the display panel comprises:
a plurality of data lines;
a plurality of scan lines, each of the scan lines comprises a main scan electrode and a branch scan electrode, the main scan electrode and the branch scan electrode of a same scan line are electrically connected, and at least a part of branch scan electrodes extend along an extending direction of a data line and are adjacent to the data line; and
a plurality of pixels, each of the pixels comprises a pixel electrode, the pixel electrode partially overlaps the branch scan electrode to form a storage capacitance;
wherein the pixel electrode partially overlaps the main scan electrode and the branch scan electrode to form the storage capacitance;
the pixel electrode partially overlaps the branch scan electrode and the main scan electrode of a fore-stage scan line;
the pixel further comprises a switching component, the switching component comprises a source electrode, a drain electrode, and a gate electrode, a parasitic capacitance Cgs is formed between the source electrode and the gate electrode;
when the display panel is in an operating state, a scan signal on each of the scan lines comprise a high level Vgh, a first low level Vgl1, and a second low level Vgl2, the high level Vgh is higher than the first low level Vgl1, the first low level Vgl1 is higher than the second low level Vgl2, the second low level Vgl2 is located on a falling edge side of the high level Vgh, and a second duration of the second low level Vgl2 is twice of or equivalent to a first duration of the high level Vgh, a high level falling edge of the scan signal on the fore-stage scan line synchronizes with a high level rising edge of the scan signal on the current-stage scan line; the storage capacitance Cst satisfies Cst=(Vgh−Vgl1)×Cgs/(Vgl1−Vgl2).

### Claim 5

A display panel, wherein the display panel comprises:
a plurality of data lines;
a plurality of scan lines, each of the scan lines comprises a main scan electrode and a branch scan electrode, the main scan electrode and the branch scan electrode of a same scan line are electrically connected, and at least a part of branch scan electrodes extend along an extending direction of a data line and are adjacent to the data line; and
a plurality of pixels, each of the pixels comprises a pixel electrode, the pixel electrode partially overlaps the branch scan electrode to form a storage capacitance;
wherein the pixel electrode partially overlaps the branch scan electrode and the main scan electrode of the fore-stage scan line;
the pixel further comprises a switching component, the switching component comprises a source electrode, a drain electrode, and a gate electrode, a parasitic capacitance Cgs is formed between the source electrode and the gate electrode;
when the display panel is in an operating state, a scan signal on each of the scan lines comprise a high level Vgh, a first low level Vgl1, and a second low level Vgl2, the high level Vgh is higher than the first low level Vgl1, the first low level Vgl1 is higher than the second low level Vgl2, the second low level Vgl2 is located on a falling edge side of the high level Vgh, and a second duration of the second low level Vgl2 is twice of or equivalent to a first duration of the high level Vgh, a high level falling edge of the scan signal on the fore-stage scan line synchronizes with a high level rising edge of the scan signal on the current-stage scan line; the storage capacitance Cst satisfies Cst=(Vgh−Vgl1)×Cgs/(Vgl1−Vgl2).