# US 11,079,433 B2 · Logic built-in self test dynamic weight selection method

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- Number: US 11,079,433 B2
- Document ID: US11079433B2
- Status: Granted
- Kind: B2
- Application number: 16/693,434
- Filed: 2019-11-25
- Published: 2021-05-27
- Granted: 2021-08-03
- Earliest claimed: 2019-11-25
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Franco Motika; Mary P. Kusko; Eugene Atwood
- Web page: https://patentgrep.com/patent/US11079433B2

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318357: {Simulation (computer simulation of digital circuits G06F30/3308)}
- G01R 31/3172: {Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing}
- G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)}
- G01R 31/31724: {Test controller, e.g. BIST state machine (for scan test G01R31/318555)}
- G01R 31/318385: {Random or pseudo-random test pattern}
- G01R 31/318566: {Comparators; Diagnosing the device under test}
- G01R 31/3187: Built-in tests
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

An approach for testing, including a self-test method, a semiconductor chip is disclosed. The approach generates test patterns, including weighted random test patterns, for testing random pattern resistant faults, and un-modeled faults directed at specific logic groups, where the dynamically generated test pattern weights are configured to optimize test coverage and test time. The dynamically generated test patterns are based on factors related to random pattern resistant logic structures interconnected via scan chains. More particularly, the dynamically generated test patterns are designed to enable fault detection within logic structures that are resistant to fault detection when tested with random patterns.

## Claims

### Claim 1

A method for testing a semiconductor chip comprising:
identifying a scan chain, of a logic circuit, of a semiconductor chip, wherein identifying the scan chain is based on: (i) logic built-in self-test (LBSIT), (ii) controls/observes logic network resistance to pseudo-random fault detection and (iii) logic design of the semiconductor chip:
generating a weighted bit chain for testing the scan chain, wherein the weighted bit chain is a pseudo-random sequence of bits, including a first pseudo-random bit, wherein a probability of the first pseudo-random bit is modified by a first weighting factor;
operating the semiconductor chip using the weighted bit chain as input to the scan chain;
determining that a fault of the logic circuit has not been tested, wherein the fault of the logic circuit has not been tested further comprises of simulating untested fault/unmodeled fault;
in response to determining that the fault of the logic circuit has not been tested, dynamically selecting a second weighting factor to generate an alternate weighted bit chain for testing the scan chain, wherein the probability of the first pseudorandom bit is modified by the second weighting factor; and
operating the semiconductor chip using the alternate weighted bit chain as input to the scan chain.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
sending, to a multiplexer integral to the semiconductor chip, a selection signal;
selecting, by the multiplexer, and based on the selection signal, a selected bit chain; and
pushing, onto the scan chain, the selected bit chain, wherein the selected bit chain is selected from the group consisting of the weighted bit chain, and the alternate weighted bit chain and wherein to push is to serially shift or load.

### Claim 3 (depends on 1)

The method of claim 1, wherein the scan chain comprises a plurality of channels, wherein each channel, of the plurality of channels, comprises a plurality of channel latches.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
determining a first weighting configuration of the weighted bit chain based on a first dynamic factor; and
determining a second weighting configuration of the weighted bit chain based on a second dynamic factor.

### Claim 5 (depends on 2)

The method of claim 2, wherein selecting the selected bit chain controls generating and applying weights by utilizing a dynamic weight selection mode selected from the group consisting of: (i) dynamic and static weight selection; (ii) channel positional based weight selection; (iii) individual channel weights selection; (iv) dynamic latch position and latch range; and (v) force “0” and force “1” selection.

### Claim 6 (depends on 5)

The method of claim 5, wherein the dynamic weight selection mode generates a weighted pattern selected from the group consisting of: (i) static weight selection per self test using ‘multiple input signature registers’ and ‘parallel shift register sequence generators’ channel (static weight selection per STUMP channel); (ii) dynamic weight selection per channel; (iii) dynamic weight selection per latch; (iv) any combination of channel per dynamic weight; (v) multiple latch positions support; and (vi) ‘hold’ dynamic channel/weight for a specified range of latch positions.

### Claim 7

A computer program product comprising a non-transitory computer readable storage medium having stored thereon program instructions programmed to perform:
identifying a scan chain, of a logic circuit, of a semiconductor chip, wherein identifying the scan chain is based on: (i) logic built-in self-test (LBSIT), (ii) controls/observes logic network resistance to pseudo-random fault detection and (iii) logic design of the semiconductor chip;
generating a weighted bit chain for testing the scan chain;
operating the semiconductor chip using the weighted bit chain as input to the scan chain;
determining that a fault of the logic circuit has not been tested;
in response to determining that the fault of the logic circuit has not been tested, dynamically selecting a second weighting factor to generate an alternate weighted bit chain for testing the scan chain, wherein the probability of the first pseudo-random bit is modified by the second weighting factor; and
operating the semiconductor chip using the alternate weighted bit chain as input to the scan chain.

### Claim 8 (depends on 7)

The computer program product of claim 7 further comprising program instructions programmed to perform:
sending, to a multiplexer integral to the semiconductor chip, a selection signal;
selecting, by the multiplexer, and based on the selection signal, a selected bit chain; and
pushing, onto the scan chain, the selected bit chain, wherein the selected bit chain is selected from the group consisting of the weighted bit chain, and the alternate weighted bit chain and wherein to push is to serially shift or load.

### Claim 9 (depends on 7)

The computer program product of claim 7, wherein the scan chain comprises a plurality of channels, wherein each channel, of the plurality of channels, comprises a plurality of channel latches.

### Claim 10 (depends on 7)

The computer program product of claim 7, further comprising program instructions programmed to perform:
determining a first weighting configuration of the weighted bit chain based on a first dynamic factor; and
determining a second weighting configuration of the weighted bit chain based on a second dynamic factor.

### Claim 11 (depends on 8)

The computer program product of claim 8, wherein selecting the selected bit chain controls generating and applying weights by utilizing a dynamic weight selection mode selected from the group consisting of: (i) dynamic and static weight selection; (ii) channel positional based weight selection; (iii) individual channel weights selection; (iv) dynamic latch position and latch range; and (v) force “0” and force “1” selection.

### Claim 12 (depends on 11)

The computer program product of claim 11, wherein the dynamic weight selection mode generates a weighted pattern selected from the group consisting of: (i) static weight selection per self test using ‘multiple input signature registers’ and ‘parallel shift register sequence generators’ channel (static weight selection per STUMP channel); (ii) dynamic weight selection per channel; (iii) dynamic weight selection per latch; (iv) any combination of channel per dynamic weight; (v) multiple latch positions support; and (vi) ‘hold’ dynamic channel/weight for a specified range of latch positions.

### Claim 13

A computer system comprising:
one or more computer processors;
one or more computer readable non-transitory storage media; and
program instructions stored on the one or more computer readable storage media for execution by at least one of the one or more computer processors, the program instructions, when executed by the one or more computer processors, causing the one or more computer processors:
to identify a scan chain, of a logic circuit, of a semiconductor chip wherein to identify the scan chain is based on: (i) logic built-in self-test (LBSIT), (ii) controls/observes logic network resistance to pseudo-random fault detection and (iii) logic design of the semiconductor chip;
to generate a weighted bit chain for testing the scan chain;
to operate the semiconductor chip using the weighted bit chain as input to the scan chain;
to determine that a fault of the logic circuit has not been tested;
in response to determine that the fault of the logic circuit has not been tested, dynamically selecting a second weighting factor to generate an alternate weighted bit chain for testing the scan chain, wherein the probability of the first pseudo-random bit is modified by the second weighting factor; and
to operate the semiconductor chip using the alternate weighted bit chain as input to the scan chain.

### Claim 14 (depends on 13)

The computer system of claim 13 further comprising program instructions programmed to perform:
to send, to a multiplexer integral to the semiconductor chip, a selection signal;
to select by the multiplexer, and based on the selection signal, a selected bit chain; and
to push, onto the scan chain, the selected bit chain, wherein the selected bit chain is selected from the group consisting of the weighted bit chain, and the alternate weighted bit chain and wherein to push is to serially shift or load.

### Claim 15 (depends on 13)

The computer system of claim 13, wherein the scan chain comprises a plurality of channels, wherein each channel, of the plurality of channels, comprises a plurality of channel latches.

### Claim 16 (depends on 13)

The computer system of claim 13, further comprising:
to determine a first weighting configuration of the weighted bit chain based on a first dynamic factor; and
to determine a second weighting configuration of the weighted bit chain based on a second dynamic factor.

### Claim 17 (depends on 14)

The computer system of claim 14, wherein selecting the selected bit chain controls generating and applying weights by utilizing a dynamic weight selection mode selected from the group consisting of: (i) dynamic and static weight selection; (ii) channel positional based weight selection; (iii) individual channel weights selection; (iv) dynamic latch position and latch range; and (v) force “0” and force “1” selection.

### Claim 18 (depends on 17)

The computer system of claim 17, wherein the dynamic weight selection mode generates a weighted pattern selected from the group consisting of: (i) static weight selection per self test using ‘multiple input signature registers’ and ‘parallel shift register sequence generators’ channel (static weight selection per STUMP channel); (ii) dynamic weight selection per channel; (iii) dynamic weight selection per latch; (iv) any combination of channel per dynamic weight; (v) multiple latch positions support; and (vi) ‘hold’ dynamic channel/weight for a specified range of latch positions.