# US 11,079,431 B2 · Entering home state after soft reset signal after address match > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,079,431 B2 - Document ID: US11079431B2 - Status: Granted - Kind: B2 - Application number: 16/410,526 - Filed: 2019-05-13 - Published: 2019-08-29 - Granted: 2021-08-03 - Earliest claimed: 2004-12-07 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Lee D. Whetsel - Web page: https://patentgrep.com/patent/US11079431B2 ## CPC - G01R 31/3172: {Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing} - G01R 31/31701: {Arrangements for setting the Unit Under Test [UUT] in a test mode} - G01R 31/31705: {Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544)} - G01R 31/31712: {Input or output aspects} - G01R 31/31713: {Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572)} - G01R 31/31722: {Addressing or selecting of test units, e.g. transmission protocols for selecting test units (for scan test G01R31/318558)} - G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)} - G01R 31/3177: Testing of logic operation, e.g. by logic analysers - G01R 31/318364: {as a result of hardware simulation, e.g. in an HDL environment (computer-aided simulation of circuits G06F30/3308)} - G01R 31/318555: {Control logic} - G01R 31/318558: {Addressing or selecting of subparts of the device under test} - G06F 11/267: Reconfiguring circuits for testing, e.g. LSSD, partitioning - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. ## Claims ### Claim 1 A process of operating an address and instruction controller having states comprising: (a) transitioning from a home state to an input address state in response to receiving a test mode select signal in a first state; (b) during the input address state, shifting address signals into an address circuit; (c) transitioning from the input address state to an address match state in response to receiving a test mode signal of a second state; (d) in the address match state, testing for a match between the address signals shifted in and an address in an address circuit; (e) transitioning from the address match state to an idle state if the address signals shifted in do not match the address in the address circuit; and (f) transitioning from the idle state to the home state in response to receiving a soft reset signal. ### Claim 2 (depends on 1) The process of claim 1 including receiving the soft reset signal from a hard and soft reset controller. ### Claim 3 (depends on 1) The process of claim 1 including maintaining the home state while the test mode select signal is in the first state. ### Claim 4 (depends on 1) The process of claim 1 including maintaining the input address state while the test mode select signal is in the second state. ### Claim 5 (depends on 1) The process of claim 1 including shifting the address signals into the address circuit with an address clock. ### Claim 6 (depends on 1) The process of claim 1 including maintaining the address match state while the test mode select signal is in the first state. ### Claim 7 (depends on 1) The process of claim 1 including maintaining the idle state while the test mode select signal is in the first or the second state. ### Claim 8 (depends on 1) The process of claim 1 in which the transitioning from the home state to an input address state includes transitioning in response to receiving the test mode select signal in the first state and a rising edge of a clock signal. ### Claim 9 (depends on 1) The process of claim 1 in which the shifting address signals into an address circuit includes shifting address signals on a rising edge of a clock signal. ### Claim 10 (depends on 1) The process of claim 1 in which the transitioning from the input address state to an address match state includes transitioning in response to receiving a test mode signal of a second state and a rising edge of a clock signal. ### Claim 11 (depends on 1) The process of claim 1 in which the testing for a match between the address signals shifted in and an address in an address circuit includes producing an address match signal indicating whether there is a match. ### Claim 12 (depends on 1) The process of claim 1 in which the testing for a match between the address signals shifted in and a local address in an address circuit includes producing an address match signal indicating whether there is a match. ### Claim 13 (depends on 1) The process of claim 1 in which the testing for a match between the address signals shifted in and a global address in an address circuit includes producing an address match signal indicating whether there is a match. ### Claim 14 (depends on 1) The process of claim 1 in which the transitioning from the address match state to an idle state includes transitioning on a rising edge of a clock signal if the address signals shifted in do not match the address in the address circuit. ### Claim 15 (depends on 1) The process of claim 1 in which each transitioning includes transitioning from one state to another state upon a rising edge of a clock signal.