# US 11,079,337 B1 · Secure wafer inspection and identification

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- Number: US 11,079,337 B1
- Document ID: US11079337B1
- Status: Granted
- Kind: B1
- Application number: 16/821,107
- Filed: 2020-03-17
- Granted: 2021-08-03
- Earliest claimed: 2020-03-17
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Fee Li Lie; Effendi Leobandung; Richard C. Johnson; Scott Halle; Robin Hsin Kuo Chao
- Web page: https://patentgrep.com/patent/US11079337B1

## CPC

- G01N 21/9501: {Semiconductor wafers (manufacturing processes per se of semiconductor devices implementing a measuring step H10P74/20)}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- G01N 21/956: Inspecting patterns on the surface of objects {(contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H10P74/20)}
- G01R 31/2831: {Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00)}
- G01R 31/318511: {Wafer Test}
- H10P 74/235: {comprising optical enhancement of defects or not-directly-visible states}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10W 46/401: {for identification or tracking}
- G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Techniques for secure and tamper-resistant wafer identification using a unique wafer fingerprint are provided. In one aspect, a method for wafer authentication includes: placing, at each level of fabrication of chips on the wafer, reference structures across the chips; inspecting the wafer at each level of the fabrication; and performing at least one of overlay and scatterometry measurements of the reference structures to use as a unique fingerprint for authenticating the wafer that has been inspected. A method for authentication throughout a process flow for fabrication of chips on a wafer is also provided, as is a wafer having chips and reference structures placed across the chips at each level of the chips to provide a unique fingerprint for authenticating the wafer.

## Claims

### Claim 1

A method for wafer authentication, the method comprising the steps of:
fabricating chips on the wafer, wherein the chips are fabricated in multiple levels on the wafer;
placing, at each level of fabrication, reference structures across the chips;
inspecting the wafer at each level of the fabrication; and
performing at least one of overlay and scatterometry measurements of the reference structures to use as a unique fingerprint for authenticating the wafer that has been inspected.

### Claim 2 (depends on 1)

The method of claim 1, wherein the reference structures are selected from the group consisting of: overlay marks, scatterometry macros, and combinations thereof.

### Claim 3 (depends on 1)

The method of claim 1, wherein the reference structures are placed on a kerf of the wafer, and wherein a placement of the reference structures is varied from one level of fabrication to another to avoid overlap of the reference structures.

### Claim 4 (depends on 1)

The method of claim 1, wherein the reference structures are placed on a chip area of the wafer, and wherein a placement of the reference structures is varied from one level of fabrication to another to avoid overlap of the reference structures.

### Claim 5 (depends on 1)

The method of claim 1, wherein the inspecting comprises:
matching the wafer to design data.

### Claim 6 (depends on 1)

The method of claim 1, wherein the overlay and scatterometry measurements are performed post etching of the wafer at each level of the fabrication.

### Claim 7 (depends on 1)

The method of claim 1, wherein the overlay and scatterometry measurements from multiple chips are used as the unique fingerprint for authenticating the wafer.

### Claim 8 (depends on 7)

The method of claim 7, further comprising the step of:
determining a chip-selection pattern for grouping the chips on the wafer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the chip-selection pattern is selected from the group consisting of: a quadrant pattern, a checkboard pattern, and a radial pattern.

### Claim 10 (depends on 1)

The method of claim 1, further comprising the steps of:
processing a level N of the wafer;
performing first overlay and scatterometry measurements of the reference structures at the level N of the wafer;
inspecting the level N of the wafer;
processing a level N+1 of the wafer;
performing second overlay and scatterometry measurements of the reference structures at the level N of the wafer; and
matching the first overlay and scatterometry measurements of the reference structures at the level N of the wafer to the second overlay and scatterometry measurements of the reference structures at the level N of the wafer for authentication.

### Claim 11 (depends on 10)

The method of claim 10, further comprising the step of:
performing third overlay and scatterometry measurements of the reference structures at the level N+1 of the wafer.

### Claim 12 (depends on 10)

The method of claim 10, further comprising the steps of:
performing lithography and etching at the level N of the wafer to process the level N of the wafer; and
performing lithography and etching at the level N+1 of the wafer to process the level N+1 of the wafer.

### Claim 13 (depends on 10)

The method of claim 10, further comprising the steps of:
performing lithography, etching, and metallization at the level N of the wafer to process the level N of the wafer; and
performing lithography, etching, and metallization at the level N+1 of the wafer to process the level N+1 of the wafer.

### Claim 14

A method for authentication throughout a process flow for fabrication of chips on a wafer, the method comprising the steps of:
processing a level N of the wafer during which reference structures are placed across the chips at the level N of the wafer;
performing first overlay and scatterometry measurements of the reference structures at the level N of the wafer;
inspecting the level N of the wafer;
processing a level N+1 of the wafer during which the reference structures are placed across the chips at the level N+1 of the wafer;
performing second overlay and scatterometry measurements at the level N+1 of the wafer of the reference structures placed at the level N of the wafer; and
matching the first overlay and scatterometry measurements of the reference structures at the level N of the wafer to the second overlay and scatterometry measurements of the reference structures at the level N of the wafer for authentication of the wafer that has been inspected.

### Claim 15 (depends on 14)

The method of claim 14, further comprising the step of:
performing third overlay and scatterometry measurements of the reference structures at the level N+1 of the wafer.

### Claim 16 (depends on 14)

The method of claim 14, further comprising the steps of:
performing lithography and etching at the level N of the wafer to process the level N of the wafer; and
performing lithography and etching at the level N+1 of the wafer to process the level N+1 of the wafer.

### Claim 17 (depends on 14)

The method of claim 14, further comprising the steps of:
performing lithography, etching, and metallization at the level N of the wafer to process the level N of the wafer; and
performing lithography, etching, and metallization at the level N+1 of the wafer to process the level N+1 of the wafer.

### Claim 18

A wafer, comprising:
chips, fabricated in multiple levels on the wafer, comprising reference structures placed across the chips at each level of fabrication, wherein the reference structures provide a unique fingerprint for authenticating the wafer when at least one of overlay and scatterometry measurements of the reference structures are performed.

### Claim 19 (depends on 18)

The wafer of claim 18, wherein the reference structures are selected from the group consisting of: overlay marks, scatterometry macros, and combinations thereof.

### Claim 20 (depends on 18)

The wafer of claim 18, wherein the reference structures are placed on at least one of a kerf of the wafer and a chip area of the wafer, and wherein a placement of the reference structures is varied from one level of fabrication to another to avoid overlap of the reference structures.