# US 11,079,336 B2 · Semiconductor inspection apparatus and semiconductor device inspection method

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- Number: US 11,079,336 B2
- Document ID: US11079336B2
- Status: Granted
- Kind: B2
- Application number: 16/808,639
- Filed: 2020-03-04
- Published: 2021-03-18
- Granted: 2021-08-03
- Earliest claimed: 2019-09-13
- Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
- Applicants: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
- Inventors: Ikuo Motonaga
- Web page: https://patentgrep.com/patent/US11079336B2

## CPC

- G01N 21/9501: {Semiconductor wafers (manufacturing processes per se of semiconductor devices implementing a measuring step H10P74/20)}
- G06T 7/0006: {using a design-rule based approach}
- G01N 21/95684: {Patterns showing highly reflecting parts, e.g. metallic elements}
- G06T 7/0004: {Industrial image inspection}
- G06T 2207/30148: Semiconductor; IC; Wafer
- G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL

## Abstract

A semiconductor inspection apparatus of embodiments includes: a light source irradiating a semiconductor package, the semiconductor package including: a sealing portion having an upper surface, a lower surface, a first side surface, and a second side surface; and a first lead extending from the first side surface, the first lead having a first wide width portion and a first narrow width portion, the first wide width portion being between the first side surface and the first narrow width portion; an imaging device capturing a first image of the first lead; a first calculator calculating a first area of a first notch region located on one side of the first narrow width portion and a second area of a second notch region located on the other side of the first narrow width portion; and a second calculator calculating a ratio of the first area and the second area.

## Claims

### Claim 1

A semiconductor inspection apparatus comprising:
a light source irradiating a semiconductor package with inspection light, the semiconductor package including: a sealing portion having an upper surface, a lower surface, a first side surface, and a second side surface facing the first side surface, the sealing portion sealing a semiconductor chip; and a first lead extending from the first side surface of the sealing portion in a first direction, the first lead having a first wide width portion and a first narrow width portion, the first wide width portion being located between the first side surface and the first narrow width portion;
an imaging device capturing a first image of the first lead, the semiconductor package being interposed between the imaging device and the light source;
a first calculator calculating a first area of a first notch region located on one side of the first narrow width portion of the first lead and a second area of a second notch region located on the other side of the first narrow width portion from the first image; and
a second calculator calculating a ratio of the first area and the second area.

### Claim 2 (depends on 1)

The semiconductor inspection apparatus according to claim 1, further comprising a third calculator,
wherein the semiconductor package includes a second lead extending from the second side surface of the sealing portion in a direction opposite to the first direction, the second lead has a second wide width portion and a second narrow width portion, and the second wide width portion is located between the second side surface and the second narrow width portion,
wherein the imaging device captures a second image of the second lead,
wherein the first calculator calculates a third area of a third notch region located on one side of the second narrow width portion of the second lead and a fourth area of a fourth notch region located on the other side of the second narrow width portion from the second image, and
wherein the third calculator calculates a first sum of the first area and the second area and a second sum of the third area and the fourth area and calculates a ratio of the first sum and the second sum.

### Claim 3 (depends on 1)

The semiconductor inspection apparatus according to claim 1, further comprising a fourth calculator calculating a first width of the first wide width portion and a second width of the first narrow width portion from the first image.

### Claim 4 (depends on 1)

The semiconductor inspection apparatus according to claim 1, further comprising a fifth calculator calculating a length of the first narrow width portion in the first direction from the first image.

### Claim 5

A semiconductor device inspection method comprising:
capturing a first image of a first lead of a semiconductor package, the semiconductor package including: a sealing portion having an upper surface, a lower surface, a first side surface, and a second side surface facing the first side surface, the sealing portion sealing a semiconductor chip; and a first lead extending from the first side surface of the sealing portion in a first direction, the first lead having a first wide width portion and a first narrow width portion, the first wide width portion being located between the first side surface and the first narrow width portion;
calculating a first area of a first notch region located on one side of the first narrow width portion of the first lead and a second area of a second notch region located on the other side of the first narrow width portion from the first image; and
calculating a ratio of the first area and the second area.

### Claim 6 (depends on 5)

The semiconductor device inspection method according to claim 5,
wherein the semiconductor package includes a second lead extending from the second side surface of the sealing portion in a direction opposite to the first direction, and the second lead has a second wide width portion and a second narrow width portion, and the second wide width portion is located between the second side surface and the second narrow width portion, and
wherein the semiconductor device inspection method further comprising:
capturing a second image of the second lead;
calculating a third area of a third notch region located on one side of the second narrow width portion of the second lead and a fourth area of a fourth notch region located on the other side of the second narrow width portion from the second image; and
calculating a first sum of the first area and the second area and a second sum of the third area and the fourth area and calculating a ratio of the first sum and the second sum.

### Claim 7 (depends on 5)

The semiconductor device inspection method according to claim 5, wherein a first width of the first wide width portion and a second width of the first narrow width portion are calculated from the first image.

### Claim 8 (depends on 5)

The semiconductor device inspection method according to claim 5, wherein a length of the first narrow width portion in the first direction is calculated from the first image.