# US 11,079,261 B2 · System on a chip with always-on processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,079,261 B2 - Document ID: US11079261B2 - Status: Granted - Kind: B2 - Application number: 16/689,555 - Filed: 2019-11-20 - Published: 2020-05-14 - Granted: 2021-08-03 - Earliest claimed: 2014-05-29 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Brijesh Tripathi; Shane J. Keil; Manu Gulati; Jung Wook Cho; Erik P. Machnicki; Gilbert H. Herbeck; Timothy J. Millet; Joshua P. de Cesare; Anand Dalal - Web page: https://patentgrep.com/patent/US11079261B2 ## CPC - G01D 9/00: Recording measured values - A61G 3/061: {using ramps} - B60P 1/433: {the loading floor or a part thereof being movable to form the ramp} - G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality - G06F 1/3287: by switching off individual functional units in the computer system - G06F 1/3293: by switching to a less power-consuming processor, e.g. sub-CPU - G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate - G01D: MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR - A61G: TRANSPORT, PERSONAL CONVEYANCES OR ACCOMMODATION SPECIALLY ADAPTED FOR PATIENTS OR DISABLED PERSONS (appliances for aiding patients or disabled persons to walk A61H3/00); OPERATING TABLES OR CHAIRS; CHAIRS FOR DENTISTRY; FUNERAL DEVICES (embalming corpses A01N1/00) - B60P: VEHICLES ADAPTED FOR LOAD TRANSPORTATION OR TO TRANSPORT, TO CARRY, OR TO COMPRISE SPECIAL LOADS OR OBJECTS (vehicles with special provisions for transporting patients or disabled persons, or their personal conveyances A61G3/00) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down. ## Claims ### Claim 1 An integrated circuit comprising: a plurality of components, wherein the plurality of components includes at least one central processing unit (CPU) processor and a memory controller configured to control a first memory; and a first component coupled to the plurality of components, wherein: the first component comprises a second memory; the first component is configured to remain powered on while the plurality of components are powered off; the first component is configured to capture a plurality of samples of sensor data from at least one sensor in a system that includes the integrated circuit, and the first component is configured write the plurality of samples to the second memory; the first component is configured to search the plurality of samples in the second memory for a predetermined pattern; the first component is configured to cause the CPU processor to be powered on in response to detecting the predetermined pattern; the first component is configured to cause the memory controller and a communication path to the memory controller from the first component to be powered on while the CPU processor remains powered off in response to the captured plurality of samples filling to a threshold level in the second memory and the first component detecting a lack of the predetermined pattern in the captured plurality of samples; the first component is configured to transfer the captured plurality of samples from the second memory to the first memory; and the first component is configured to cause the plurality of components to be powered on responsive to the at least one sensor detecting a predetermined event separate from the plurality of samples. ### Claim 2 (depends on 1) The integrated circuit as recited in claim 1 wherein the predetermined event is a user interaction with user interface device. ### Claim 3 (depends on 2) The integrated circuit as recited in claim 2 wherein the user interface device is a button, and wherein the predetermined event comprises a pressing of the button. ### Claim 4 (depends on 1) The integrated circuit as recited in claim 1 wherein the first component further comprises a first processor that is powered on in response to the predetermined event, and wherein the first processor is configured to initiate the power on of the plurality of components. ### Claim 5 (depends on 4) The integrated circuit as recited in claim 4 wherein the first processor is configured to search the plurality of samples for the predetermined pattern. ### Claim 6 (depends on 5) The integrated circuit as recited in claim 5 wherein the first processor is power gated at times other than times in which the first processor is searching the plurality of samples for the predetermined pattern and times in which the first processor is causing the power on of the plurality of components. ### Claim 7 (depends on 4) The integrated circuit as recited in claim 4 wherein the first component further comprises a sensor capture circuit configured to capture a plurality of samples of sensor data from the sensor and write the plurality of samples to the second memory, and wherein the first component is configured to operate at a plurality of power states, and wherein a first power state of the plurality of power states includes the sensor capture circuit being powered on and capturing the plurality of samples of sensor data while the first processor is powered off. ### Claim 8 (depends on 7) The integrated circuit as recited in claim 7 wherein a second power state of the plurality of power states includes the first processor being powered on to perform processing of the plurality of samples or to cause powering on of the plurality of components in response to the predetermined event. ### Claim 9 (depends on 8) The integrated circuit as recited in claim 8 wherein the first component is configured to transition from the first power state to the second power state responsive to detecting the predetermined event. ### Claim 10 (depends on 9) The integrated circuit as recited in claim 9 wherein the first component is configured to transition from the first power state to the second power state responsive to a number of the plurality of samples in the second memory reaching a predetermined amount. ### Claim 11 A method comprising: capturing a plurality of samples of sensor data from at least one sensor in a system that includes an integrated circuit, wherein the integrated circuit comprises a plurality of components, wherein the plurality of components includes at least one central processing unit (CPU) processor and a memory controller configured to control a first memory, and wherein the integrated circuit comprises a first component coupled to the plurality of components, wherein the first component is configured to remain powered on while the plurality of components are powered off, and wherein the first component comprises a second memory, and wherein the first component is configure to perform the capturing; writing the plurality of samples to the second memory by the first component; searching the plurality of samples in the second memory by the first component for a predetermined pattern; causing the CPU processor to be powered on by the first component in response to detecting the predetermined pattern; causing the memory controller and a communication path to the memory controller from the first component to be powered on by the first component while the CPU processor remains powered off in response to the captured plurality of samples filling to a threshold level in the second memory and the first component detecting a lack of the predetermined pattern in the captured plurality of samples; transferring the captured plurality of samples from the second memory to the first memory; and causing the plurality of components to be powered on by the first component responsive to the at least one sensor detecting a predetermined event separate from the plurality of samples. ### Claim 12 (depends on 11) The method as recited in claim 11 wherein the predetermined event is a user interaction with user interface device. ### Claim 13 (depends on 12) The method as recited in claim 12 wherein the user interface device is a button, and wherein the predetermined event comprises a pressing of the button. ### Claim 14 (depends on 11) The method as recited in claim 11 wherein the first component further comprises a first processor that is powered on in response to the predetermined event, and wherein causing the plurality of components to be powered on is performed by the first processor. ### Claim 15 (depends on 14) The method as recited in claim 14 wherein searching the plurality of samples for the predetermined pattern is performed by the first processor. ### Claim 16 (depends on 15) The method as recited in claim 15 further comprising power gating the first processor at times other than times in which the first processor is searching the plurality of samples for the predetermined pattern and times in which the first processor is causing power on of the plurality of components. ### Claim 17 (depends on 14) The method as recited in claim 14 wherein the first component is configured to operate at a plurality of power states, and wherein a first power state of the plurality of power states includes capturing the plurality of samples sensor data while the first processor is powered off, and wherein a second power state of the plurality of power states includes the first processor being powered on to perform processing of the plurality of samples or causing the plurality of components to be powered up of the predetermined event. ### Claim 18 (depends on 17) The method as recited in claim 17 further comprising transitioning, but the first component, from the first power state to the second power state responsive to detecting the predetermined event. ### Claim 19 (depends on 18) The method as recited in claim 18 further comprising transitioning, by the first component, from the first power state to the second power state responsive to a number of the plurality of samples in the second memory reaching a predetermined amount. ### Claim 20 A system comprising: at least one sensor; an external memory; and a system on a chip (SOC) comprising a plurality of components, wherein the plurality of components includes at least one central processing unit (CPU) processor and a memory controller configured to control a first memory, and the SOC further comprising a first component coupled to the plurality of components, wherein: the first component comprises a second memory, the first component is configured to remain powered on while the plurality of components are powered off, the first component is configured to capture a plurality of samples of sensor data from the at least one sensor, and the first component is configured write the plurality of samples to the second memory, the first component is configured to search the plurality of samples in the second memory for a predetermined pattern, the first component is configured to cause the CPU processor to be powered on in response to detecting the predetermined pattern, the first component is configured to cause the memory controller and a communication path to the memory controller from the first component to be powered on while the CPU processor remains powered off in response to the captured plurality of samples filling to a threshold level in the second memory and the first component detecting a lack of the predetermined pattern in the captured plurality of samples, the first component is configured to transfer the captured plurality of samples from the second memory to the first memory, and the first component is configured to cause the plurality of components to be powered on responsive to the at least one sensor detecting a predetermined event separate from the plurality of samples.