Maximum voltage selector for power management applications

A voltage switching circuit, comprising:

• a comparator connected to receive first and second power supplies, where the comparator is configured to generate a comparator activation signal when the comparator is ready to operate and to generate a first selection signal identifying which of the first and second power supplies is higher;
• an active maximum voltage switching circuit connected to receive the first and second power supplies, where the active maximum voltage switching circuit is configured to generate a maximum bias voltage which is the higher of the first and second power supplies;
• a first level shifter connected to receive the comparator activation signal, where the first level shifter is configured to generate first and second level-shifted comparator activation signals;
• a gate driver circuit connected to receive the first and second power supplies, where the gate driver circuit is configured to generate first and second PMOS gate control signals only in response to the first and second level-shifted comparator activation signals by using the first selection signal to generate first and second overlapping phase signals which control timing of the first and second PMOS gate control signals so that a ground voltage is supplied as the first PMOS gate control signal only after the maximum bias voltage is supplied as the second PMOS gate control signal;
• first and second PMOS power transistors for connecting the first and second power supplies, respectively, to a power supply output in response to the first or second PMOS gate control signals provided, respectively, to gate terminals of the first and second PMOS power transistors;
• and
• a bias switching circuit connected to bias an n-well of each of the first and second PMOS power transistors to avoid forward biased junction diodes by connecting the n-well of each of the first and second PMOS power transistors to either the maximum bias voltage or one of the first and second power supplies in response to the first and second level-shifted comparator activation signals.

A method of controlling a dual power supply on an integrated circuit chip, comprising:

• receiving first and second power supply voltages;
• comparing the first and second power supply voltage at a comparator to generate a comparator activation signal when the comparator is ready to operate;
• generating a first selection signal at the comparator to identify which of the first and second power supply voltages is higher;
• remapping the first and second power supply voltages into a maximum bias voltage which is the higher of the first and second power supply voltages;
• generating first and second PMOS gate control signals in response to the comparator activation signal by using the first selection signal to generate first and second overlapping phase signals which control timing of the first and second PMOS gate control signals so that a ground voltage is supplied as the first power PMOS gate control signal only after the maximum bias voltage is supplied as the second PMOS gate control signal in response to the comparator activation signal;
• and
• applying the first and second PMOS gate control signals to gate terminals of first and second PMOS power transistors to connect the first and second power supply voltages, respectively, to a power supply output in response to the first or second PMOS gate control signals provided, respectively, to gate terminals of the first and second PMOS power transistors while biasing an n-well of each of the first and second PMOS power transistors to avoid forward biased junction diodes by connecting the n-well of each of the first and second PMOS power transistors to either the maximum bias voltage or one of the first and second power supply voltages in response to the comparator activation signal, thereby generating a maximum output supply voltage at the power supply output.