Physical hardware clock chaining

A computer apparatus, comprising:

• a first network interface controller including:
• at least one first network interface port configured to transfer data with a first packet-data network (PDN), the first PDN including a master clock configured to provide a clock synchronization signal S1;
• a first connector configured to be connected to a connection;
• a first physical hardware clock (PHC) configured to maintain a time value T1 responsively to the clock synchronization signal S1;
• and
• a first clock controller configured to:
• generate a clock synchronization signal S2 responsively to the received clock synchronization signal S1, the clock synchronization signal S2 having a frequency, which is set responsively to the received clock synchronization signal S1;
• and send the clock synchronization signal S2 over the first connector and over the connection to a second network interface controller;
• and
• the second network interface controller including:
• at least one second network interface port configured to transfer data with a second PDN different from the first PDN;
• a second connector configured to be connected to the connection;
• a second PHC;
• and
• a second clock controller configured to:
• receive the clock synchronization signal S2 from the second connector;
• update the second PHC with a time value T2 responsively to the received clock synchronization signal S2;
• send another clock synchronization signal to network nodes in the second PDN responsively to the time value T2 such that the second network interface controller is configured to act as a master clock in the second PDN.