Method and apparatus for implementing multirate SerDes systems
AssigneeMellanox Technologies, Ltd.
InventorsHananel Faig, Adam Kaminer, David (Dima) Rochlin, Raanan Ivry
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Abstract
A method for providing back-compatibility for rational sampling rate disparities between two circuitries, comprises: a) providing a Phase Locked Loop (PLL) operating at a rate different than that of the Symbols generator, which is coupled to a Digital to Analog Converter (DAC) or an Analog to Digital Converter (ADC); b) providing an interpolation filter coupled to said converter, which filter is adapted to perform sampling rate conversion operations on the samples using zero-stuffing, filtering, and decimation, or the like computation-saving algorithm; and c) obtaining the sampling of the symbols at the required and compatible rate.
Claims17
A method for providing back-compatibility for rational sampling rate disparities between circuitries, the method comprising:
- generating, by a symbols generator, a stream of symbols at a symbol rate;
- generating, by a digital filter connected with the symbols generator, a stream of digital samples having the symbol rate;
- converting, by an interpolation filter coupled with the digital filter, the stream of digital samples from the symbol rate to a sampling rate, wherein the sampling rate is greater than the symbol rate;
- and
- sampling, by
- a Digital to Analog Converter (DAC), the stream of digital samples at the sampling rate, wherein a Phase Locked Loop (PLL) coupled with the DAC is configured to cause sampling by the DAC at a fixed frequency as defined by the sampling rate.
A system for providing back-compatibility for rational sampling rate disparities between circuitries, the system comprising:
- a symbols generator configured to generate a stream of symbols at a symbol rate;
- a digital filter configured to receive the stream of symbols at the symbol rate and generate a stream of digital samples having the symbol rate;
- an interpolation filter coupled with the digital filter;
- a Digital to Analog Converter (DAC) coupled with the interpolation filter;
- and
- a Phase Locked Loop (PLL) coupled with the DAC and operating at a sampling rate that is greater than the symbol rate, wherein the PLL is configured to cause sampling by the DAC at a fixed frequency as defined by the sampling rate,
- wherein the interpolation filter is configured to convert the stream of digital samples from the symbol rate to the sampling rate for use by the DAC.
A system for providing back-compatibility for rational sampling rate disparities between circuitries, the system comprising:
- an Analog to Digital Converter (ADC) configured to receive a stream of samples;
- a Phase Locked Loop (PLL) coupled with the ADC and configured to cause sampling of the stream of samples by the ADC at a fixed frequency as defined by a sampling rate;
- an interpolation filter coupled with the ADC, wherein the interpolation filter is configured to convert the stream of samples from the sampling rate to a symbol rate, wherein the symbol rate is less than the sampling rate;
- and
- a digital signal processer (DSP) configured to receive the stream of samples at the symbol rate and recover a sequence of signals associated with the stream of samples.
Dependencies are inferred from the claim text.