Phase control block for managing multiple clock domains in systems with frequency offsets

A method of receiving a digital signal comprising:

• providing a first clock signal having a first phase to a data sampler and obtaining a first plurality of samples of the digital signal from the data sampler;
• providing a second clock signal having a second phase to an edge sampler, and obtaining a second plurality of samples of the digital signal from the edge sampler;
• temporarily storing in temporary storage the first plurality of samples from the data sampler and the second plurality of samples from the edge sampler;
• using the first clock signal and second clock signal:
• generating, based on the first plurality of samples and second plurality of samples in the temporary storage, a sequence of values indicating whether the first clock signal is early or late relative to transitions in the digital signal, wherein generating the sequence of values includes comparing neighboring samples in the first plurality of samples of the digital signal and comparing samples in the first plurality of samples of the digital signal with samples in the second plurality of samples of the digital signal, and based on results of the comparisons, generating the sequence of values indicating whether the first clock signal is early or late relative to transitions in the digital signal;
• and
• providing phase correction information based on the generated sequence of values;
• and
• adjusting the first phase of the first clock signal and second phase of the second clock signal based on the phase correction information.

A circuit for receiving a digital signal comprising:

• data sampling means having a data sampler clock input, the data sampling means to receive the digital signal;
• edge sampling means having an edge sampler clock input, the edge sampling means to receive the digital signal;
• clock signal supply means for providing a first clock signal having a first phase to the data sampler clock input of the data sampling means and a second clock signal having a second phase to the edge sampler clock input of the edge sampling means;
• temporary storage means for receiving and storing a first plurality of samples of the digital signal sampled by the data sampler and a second plurality of samples of the digital signal sampled by the edge sampler;
• and
• digital phase detector means, coupled to the temporary storage means, for:
• generating a sequence of values indicating whether the first clock signal is early or late relative to transitions in the digital signal, wherein generating the sequence of values includes comparing neighboring samples in the first plurality of samples of the digital signal and comparing samples in the first plurality of samples of the digital signal with samples in the second plurality of samples of the digital signal, and based on results of the comparisons, generating the sequence of values indicating whether the first clock signal is early or late relative to transitions in the digital signal;
• and
• providing phase correction information based on the generated sequence of values;
• wherein the clock signal supply means is operative to selectively vary the first and second phases based on the phase correction information.