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US 11,057,587 B2Granted
Compositing video signals and stripping composite video signal
AssigneeHangzhou Hikvision Digital Technology Co., Ltd.
InventorHailong Zhang
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Abstract
A method of compositing video signals includes: obtaining at least two video signals to be composited; determining a multiplier point mode corresponding to each of the at least two video signals; performing a byte size adjustment on the at least two video signals respectively according to the multiplier point mode corresponding to each of the at least two video signals; performing a composite modulation on bytes corresponding to the at least two video signals after the byte size adjustment, and outputting composite-modulated data through a target signal interface of an analog-to-digital conversion chip.
Claims18
A method comprising:
- obtaining, by an analog-to-digital conversion chip in an electronic device, at least two video signals to be composited, wherein the analog-to-digital conversion chip is configured with a target signal interface configured to transmit digital video streams, wherein a working clock frequency of the target signal interface is a predetermined clock frequency, and a target byte size is single-edge sampled at the predetermined clock frequency;
- and
- compositing, by the analog-to-digital conversion chip, the at least two video signals by
- determining a multiplier point mode corresponding to each of the at least two video signals, wherein a multiplier point mode corresponding to each of the video signals enables the video signal to have a target byte size within a unit time duration;
- performing a byte size adjustment on the at least two video signals respectively according to the multiplier point mode corresponding to each of the at least two video signals to obtain at least two video signals after the byte size adjustment;
- and
- performing a composite modulation on bytes corresponding to the at least two video signals after the byte size adjustment to obtain composite-modulated data, and outputting the composite-modulated data through the target signal interface of the analog-to-digital conversion chip.
4 more elements
An apparatus comprising:
- an analog-to-digital conversion chip for compositing video signals;
- and
- a target signal interface configured with the analog-to-digital conversion chip, wherein the target signal interface is configured to transmit digital video streams, and wherein a working clock frequency of the target signal interface is a predetermined clock frequency, and a target byte size is single-edge sampled at the predetermined clock frequency,
- wherein the analog-to-digital conversion chip comprises:
- a video signal obtainer configured to obtain at least two video signals to be composited;
- a multiplier point mode determiner configured to determine a multiplier point mode corresponding to each of the at least two video signals, wherein a multiplier point mode corresponding to each of the video signals enables the video signal to have a target byte size within a unit time duration;
- a byte size adjuster configured to perform a byte size adjustment on the at least two video signals respectively according to the multiplier point mode corresponding to each of the at least two video signals to obtain at least two video signals after the byte size adjustment;
- and
- a modulation processor configured to perform a composite modulation on bytes corresponding to the at least two video signals after the byte size adjustment to obtain composite-modulated data, and output the composite-modulated data through the target signal interface of the analog-to-digital conversion chip.
6 more elements
An electronic device, comprising:
- an analog-to-digital conversion chip, configured with a first target signal interface for transmitting first digital video streams, wherein a first working clock frequency of the first target signal interface is a first predetermined clock frequency, and a first target byte size is single-edge sampled at the first predetermined clock frequency;
- and
- a system-on-chip (SOC) chip, configured with a second target signal interface for transmitting second digital video streams, wherein a second working clock frequency of the second target signal interface is a second predetermined clock frequency, and a second target byte size is single-edge sampled at the second predetermined clock frequency;
- wherein the analog-to-digital conversion chip is configured to:
- obtain at least two video signals to be composited,
- determine a multiplier point mode corresponding to each of the at least two video signals, wherein a multiplier point mode corresponding to at least one of the at least two video signals enables the video signal to have a target byte size within a unit time duration,
- perform a first byte size adjustment on the at least two video signals respectively according to the multiplier point mode corresponding to each of the at least two video signals to obtain at least two video signals after the first byte size adjustment,
- perform a composite modulation on bytes corresponding to the at least two video signals after the byte size adjustment to obtain composite-modulated data, and
- output the composite-modulated data to the SOC chip through the first target signal interface, and
- wherein the SOC chip is configured to:
- receive the composite-modulated data through the second target signal interface,
- single-edge or double-edge sample the composite-modulated data to obtain the at least two particular video signals after second byte size adjustment,
- determine a multiplier point mode corresponding to each of the at least two particular video signals after the second byte size adjustment, and
- perform signal stripping on the at least two particular video signals after the second byte size adjustment according to the multiplier point mode corresponding to each of the at least two particular video signals to obtain the at least two video signals before the first byte size adjustment.
11 more elements
Dependencies are inferred from the claim text.