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US 11,057,044 B2Granted
Time-interleaved analog-to-digital converter with calibration
AssigneeIntel Corporation
InventorCho-Ying Lu
Life of this patent
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Abstract
An apparatus is provided to calibrate an analog-to-digital converter (ADC). The apparatus includes a calibration circuitry coupled to an output of the ADC, wherein the calibration circuitry is to identify a maximum value and minimum value of the output of the ADC, and is to calibrate one or more performance parameters of the ADC according to the maximum and minimum values. The performance parameters include: gain of the ADC, offset of the ADC, and timing skew between the ADC and a neighboring ADC.
Claims20
An apparatus comprising:
- an analog-to-digital converter (ADC) having a first input to receive an analog signal and an output to provide a digital representation of the analog signal;
- and
- a calibration circuitry having an input coupled to an output of the ADC, wherein the calibration circuitry includes a multiplexer coupled to the output of the ADC, wherein the multiplexer is to select between a first calibration mode and second calibration mode wherein an output of the calibration circuitry is coupled to a second input of the ADC, and wherein the output of the calibration circuitry is to adjust a delay of a sampling clock to the ADC.
An apparatus comprising:
- a first an analog-to-digital converter (ADC) having an input to receive a first analog signal and an output to provide a first digital representation of the first analog signal;
- a second ADC having an input to receive a second analog signal and an output to provide a second digital representation of the second analog signal;
- a first calibration circuitry;
- and
- a second calibration circuitry, wherein the first calibration circuitry is to receive the first digital representation and an output of the second calibration circuitry, wherein the first calibration circuitry is to generate a first sampling control for the first ADC, wherein the second calibration circuitry is to receive the second digital representation and an output of a third calibration circuitry, and wherein the second calibration circuitry is to generate a second sampling control for the second ADC.
2 more elements
A system comprising:
- a memory;
- a processor coupled to the memory;
- and
- a wireless interface communicatively coupled to the processor, wherein the processor includes:
- an analog-to-digital converter (ADC) having a first input to receive an analog signal and an output to provide a digital representation of the analog signal;
- and
- a calibration circuitry having an input coupled to an output of the ADC, wherein the calibration circuitry includes a multiplexer coupled to the output of the ADC, wherein the multiplexer is to select between a first calibration mode and second calibration mode, wherein an output of the calibration circuitry is coupled to a second input of the ADC, and wherein the output of the calibration circuitry is to adjust a delay of a sampling clock to the ADC.
4 more elements
Dependencies are inferred from the claim text.