Phase-locked loop circuit and clock generator including the same

A phase-locked loop (PLL) circuit comprising:

• a voltage-controlled oscillator configured to generate an output clock signal;
• a sub-sampling PLL circuit configured to receive the output clock signal as a feedback signal and based thereon perform a fractional frequency division-based phase locking operation;
• and
• a fractional frequency division control circuit configured to:
• provide a selection reference clock signal for the fractional frequency division-based phase locking operation to the sub-sampling PLL circuit;
• generate delay information regarding a constant delay time within one cycle of the feedback signal by performing a delay operation using the feedback signal when the feedback signal has a first frequency;
• generate a plurality of delay reference clock signals gradually delayed by up to the delay time by using a reference clock signal having a second frequency, based on the delay information;
• and
• generate the selection reference clock signal using the plurality of delay reference clock signals.

A clock generator comprising:

• a voltage-controlled oscillator configured to generate an output clock signal;
• an auxiliary phase-locked loop (PLL) circuit configured to perform an integer frequency division-based phase locking operation on the output clock signal;
• a sub-sampling PLL circuit configured to perform a fractional frequency division-based phase locking operation on the output clock signal after the integer frequency division-based phase locking operation;
• and
• a fractional frequency division control circuit configured to provide a selection reference clock signal for the fractional frequency division-based phase locking operation to the sub-sampling PLL circuit,
• wherein the fractional frequency division control circuit comprises:
• a voltage-controlled delay line configured to route a feedback signal to generate delay information;
• a replica voltage-controlled delay line to which the delay information is applied, comprising the same characteristics as the voltage-controlled delay line, and configured to route a reference clock signal to generate a plurality of delay reference clock signals delayed by up to a different respective delay time;
• and
• a digital-to-time converter (DTC) configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.