Clock divider with quadrature error correction
AssigneeInternational Business Machines Corporation
InventorsMarcel A. Kossel, Vishal Khatri, Pier Andrea Francese, Matthias Braendli
Life of this patent
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Abstract
The present disclosure relates to a method for quadrature error correction using a frequency divider circuit. The method comprises delaying input of data to master input terminals and/or slave input terminals of the frequency divider circuit for correcting a quadrature error between the in-phase and quadrature-phase output signals.
Claims11
A frequency divider circuit comprising:
- a master and slave latch connected in series and having a feedback path, the master latch including a master reading branch with first input terminals and a master latching branch with quadrature output signals, the slave latch including a slave reading branch with second input terminals and a slave latching branch with in-phase output signals;
- a first current supplying circuit for supplying a first current to the master reading branch and the master latching branch;
- a second current supplying circuit for supplying a second current to the slave latching branch and the slave reading branch;
- and
- a current steering circuit for connecting the first current supplying circuit to the master reading branch and connecting the second current supplying circuit to the slave latching branch in response to a first clock signal;
- and connecting the second current supplying circuit to the slave reading branch and connecting the first current supplying circuit to the master latching branch in response to a second clock signal;
- wherein the frequency divider circuit is configured for delaying input of data to the first and/or second input terminals for correcting a quadrature error between the quadrature and in-phase output signals.
A method for quadrature error correction using a frequency divider circuit, the frequency divider circuit comprising a master and slave latch connected in series and having a feedback path, the master latch including a master reading branch with first input terminals and a master latching branch with quadrature output signals, the slave latch including a slave reading branch with second input terminals and a slave latching branch with in-phase output signals;
- a first current supplying circuit for supplying a first current to the master reading branch and the master latching branch;
- a second current supplying circuit for supplying a second current to the slave latching branch and the slave reading branch;
- a current steering circuit for connecting the first current supplying circuit to the master reading branch and connecting the second current supplying circuit to the slave latching branch in response to a first clock signal;
- and connecting the second current supplying circuit to the slave reading branch and connecting the first current supplying circuit to the master latching branch in response to a second clock signal;
- the method comprising:
- delaying input of data to the first and/or second input terminals for correcting a quadrature error between the quadrature and in-phase output signals.
Dependencies are inferred from the claim text.