Semiconductor device including buffer circuit
AssigneeMicron Technology, Inc.
InventorsTetsuya Arai, Shuichi Tsukada, Junki Taniguchi
Life of this patent
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Abstract
A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.
Claims16
An apparatus, comprising:
- a power supply line;
- an output terminal;
- a circuit configured to receive a plurality of first control signals and a data signal, the circuit configured to provide a first portion of the plurality of first control signals and further configured to provide a selection signal based on the data signal, wherein the circuit is further configured to provide a second control signal based on a second portion of the plurality of first control signals and the data signal, wherein the circuit comprises a buffer configured to receive the data signal, to buffer the received data signal, and further configured to provide the buffered data signal as the selection signal;
- a driver coupled between the power supply line and the output terminal, the driver configured to receive the selection signal and the first portion of the plurality of first control signals.
An apparatus comprising:
- a calibration circuit configured to provide an impedance code including first and second control signals;
- and
- a circuit configured to receive a data signal and the impedance code, and further configured to provide a selection signal based on the data signal, the first control signal, and a third control signal based on a combination of the data signal and the second control signal;
- wherein the circuit further includes a buffer configured to receive the data signal, configured to buffer the received data signal, and further configured to provide a buffered data signal.
An apparatus comprising:
- a driver strength selector configured to receive a first data signal and further configured to provide a second data signal;
- an impedance selector configured to receive a plurality of control signals and the second data signal, the impedance selector configured to provide a first portion of the plurality of control signals and further configured to provide a selection signal based on the second data signal.
Dependencies are inferred from the claim text.