Reliability in start up sequence for D-mode power FET driver
AssigneepSemi Corporation
InventorsArezu Bagheri, Buddhika Abesingha
Life of this patent
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Abstract
Methods and devices to address start up of half-bridge circuits including D-mode power FETs are disclosed. The disclosed devices overcome possible issues of output overload or excess current through gate-source of power FETs during start up. Voltage monitoring is used to address the issue of output overload and pre-charging of coupling capacitors are described as solutions to uncontrolled pre-charging of coupling capacitors. Pre-charging of coupling capacitors are implemented using current sources.
Claims23
An electronic circuit configured to receive an input DC voltage, the electronic circuit comprising:
- a high side driver, and a low side driver;
- a high side depletion mode field effect transistor (FET) and a low side depletion mode FET;
- a high side coupling capacitor coupling the high side driver to the high side depletion mode FET, and a low side coupling capacitor coupling the low side driver to the low side depletion mode FET;
- an FET switch configured to couple the input DC voltage to the high side depletion mode FET;
- a bypass capacitor connected to the FET switch and the high side depletion mode FET at one end and to a reference voltage at another end;
- wherein in a first state:
- the FET switch is in an OFF state, thereby electrically isolating the input DC voltage from the high side depletion mode FET, and
- the electronic circuit charges the high side coupling capacitor and the low side coupling capacitor according to a comparison of the bypass capacitor voltage with a threshold voltage, thereby keeping the high side depletion mode FET and the low side depletion mode FET in an OFF state.
An electronic circuit configured to receive an input DC voltage, the electronic circuit comprising:
- a high side driver, and a low side driver;
- a high side depletion mode (D-mode) field effect transistor (FET) and a low side depletion mode (D-mode) FET;
- a high side coupling capacitor coupling the high side driver to the high side D-mode FET, and a low side coupling capacitor coupling the low side driver to the low side D-mode FET;
- an FET switch configured to couple the input DC voltage to the high side D-mode FET;
- a bypass capacitor connected to the FET switch and the high side depletion mode FET at one end and to a reference voltage at another end;
- a high side capacitor coupled across the high side driver and a low side capacitor coupled across the low side driver;
- a first current source connected to the high side capacitor at one end and to the high side coupling capacitor at another end;
- and
- a second current source connected to the low side capacitor at one end and to the low side coupling capacitor at another end,
- wherein in a first state:
- the FET switch is in an OFF state, thereby electrically isolating the input DC voltage from the high side depletion mode FET:
- the first current source is in an ON state and configured to charge the high side coupling capacitor, thereby enabling the high side driver to control the high side depletion mode FET to be in an OFF state;
- and
- the second current source is in an ON state and configured to charge the low side coupling capacitor, thereby enabling the low side driver to control the low side depletion mode FET to be in an OFF state.
A method of starting up a circuit configured to receive an input DC voltage, the circuit comprising
- a high side depletion mode FET connected to a low side depletion mode FET at a switch node;
- a high side coupling capacitor connected to the high side depletion mode FET at one end and to a first current source at another end;
- a low side coupling capacitor connected to the low side depletion mode FET at one end and to a second current source at another end;
- and
- an FET switch connectable to the input DC voltage at a first end and to the high side depletion mode FET at a second end,
- the method comprising:
- turning the FET switch off;
- monitoring a DC voltage at the second end;
- based on the monitoring, when the DC voltage at the second end is less than a set threshold voltage:
- turning the first current source on, thereby charging the high side coupling capacitor thereby enabling control of the high side depletion mode FET to be in an OFF state;
- and
- turning the second current source on, thereby charging the low side coupling capacitor thereby enabling control of the low side depletion mode FET to be in an OFF state.
Dependencies are inferred from the claim text.