US 11,057,028 B2 · Double clock architecture for small duty cycle DC-DC converter

Abstract

A DC-DC converter includes clock generation circuitry generating first and second clock signals that are out of phase, and a control signal generator generating a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage. Boost circuitry charges an energy storage component during an on-phase and discharges the energy storage component during an off-phase to thereby generate an output voltage. The on-phase and off-phase are set as a function of the switching control signal. Sum voltage generation circuitry generates a ramp voltage in response to an edge of the first clock signal and generates the summed voltage at an edge of the second clock signal. The sum voltage represents a sum of the ramp voltage and a voltage representative of the current flowing in the energy storage component during the on-phase.

Claims26

Dependent claims

A DC-DC converter boosting an input voltage to an output voltage, the DC-DC converter comprising:

clock generation circuitry configured to generate first and second clock signals that are out of phase with each other;
a control signal generator configured to generate a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage;
boost circuitry configured to charge an energy storage component during an on-phase and to discharge the energy storage component during an off-phase to thereby generate the output voltage, wherein the on-phase and off-phase are set as a function of the switching control signal;
and
sum voltage circuitry configured to:
generate a ramp voltage based upon the first clock signal;
and
from a falling edge of the second clock signal until an end of the on-phase, generate the summed voltage to represent a sum of the ramp voltage and a voltage representative of a current signal carrying information about a storage component current flowing in the energy storage component during the on-phase, but from a beginning of the off-phase until a next falling edge of the second clock signal, generate the summed voltage to represent only the ramp voltage, the off-phase beginning at the end of the on-phase.

5 more elements

A DC-DC converter boosting an input voltage to an output voltage, the DC-DC converter comprising:

clock generation circuitry configured to generate first and second clock signals that are out of phase with each other;
a control signal generator configured to generate a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage;
boost circuitry configured to charge an energy storage component during an on-phase and to discharge the energy storage component during an off-phase to thereby generate the output voltage, wherein the on-phase and off-phase are set as a function of the switching control signal;
and
sum voltage circuitry configured to:
generate a ramp voltage;
and
generate the summed voltage at an edge of the second clock signal, the sum voltage representing a sum of the ramp voltage and a voltage representative of a current signal carrying information about a storage component current flowing in the energy storage component during the on-phase;
wherein the boost circuitry is coupled to the energy storage component at an intermediate node;
and
wherein the sum voltage circuitry comprises:
a first voltage to current converter circuit configured to convert the ramp voltage to a ramp current;
a second voltage to current converter circuit configured to convert a voltage at the intermediate node to the current signal, in response to the edge of the second clock signal;
a summing junction configured to sum the ramp current and the current signal to produce a summed current;
and
a branch or element configured to convert the summed current to the summed voltage.

13 more elements

A DC-DC converter boosting an input voltage to an output voltage, the DC-DC converter comprising:

clock generation circuitry configured to generate first and second clock signals that are out of phase with each other;
a control signal generator configured to generate a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage;
boost circuitry configured to charge an energy storage component during an on-phase and to discharge the energy storage component during an off-phase to thereby generate the output voltage, wherein the on-phase and off-phase are set as a function of the switching control signal;
and
sum voltage circuitry configured to:
generate a ramp voltage;
and
generate the summed voltage at an edge of the second clock signal, the sum voltage representing a sum of the ramp voltage and a voltage representative of a current signal carrying information about a storage component current flowing in the energy storage component during the on-phase;
wherein the boost circuitry is coupled to the energy storage component at an intermediate node;
wherein the boost circuitry comprises:
a low side transistor configured to couple the intermediate node to ground during the on-phase;
and
a high side transistor configured to couple the intermediate node to a load to produce the output voltage during the off-phase;
a digital controller configured to generate a low side on signal as being asserted during the on-phase and to generate a high side on signal as being asserted during the off-phase to thereby set a switching duty cycle, in response to the switching control signal;
and
a gate driver configured to turn on the low side transistor during the on-phase but turn off the low side transistor during the off-phase, and to turn on the high side transistor during the off-phase but turn off the high side transistor during the on-phase.

13 more elements

A DC-DC converter boosting an input voltage at an input to an output voltage at an output, the DC-DC converter comprising:

an energy storage component coupled between the input voltage and an intermediate node;
a control signal generator configured to provide a switching control signal based upon a comparison of an error voltage to a sum voltage, the sum voltage being a function of a ramp voltage and a voltage representative of a current signal carrying information about a storage component current flowing in the energy storage component during an on-phase, the error voltage being representative of a difference between a desired operating point and the output voltage;
boost circuitry configured to charge the energy storage component during the on-phase and to discharge the energy storage component during an off-phase to thereby generate the output voltage, wherein the on-phase and off-phase are set as a function of the switching control signal;
and
sum voltage circuitry configured to generate the sum voltage, the sum voltage circuitry comprising:
a ramp voltage generator configured to:
cause a ramp voltage to rise, in response to a falling edge of a first clock signal;
and
cause the ramp voltage to fall, in response to a rising edge of the first clock signal;
a first voltage to current converter circuit configured to convert the ramp voltage to a ramp current;
a second voltage to current converter circuit configured to convert a voltage at the intermediate node to the current signal, in response to a falling edge of a second clock signal, the second clock signal being out of phase with the first clock signal;
and
a branch or element configured to generate the sum voltage based upon a sum of the ramp current and the current signal;
wherein the causing of the ramp voltage to rise by the ramp voltage generator in response to the falling edge of the first clock signal results in settling of the ramp current prior to the falling edge of the second clock signal.

11 more elements

Dependencies are inferred from the claim text.

Double clock architecture for small duty cycle DC-DC converter

Life of this patent

Double clock architecture for small duty cycle DC-DC converter

Life of this patent

Abstract

Claims26