Semi-dynamic flip-flop implemented as multi-height standard cell and method of designing integrated circuit including the same

A semi-dynamic flip-flop, comprising:

• a semiconductor substrate;
• a first power rail, a second power rail, a third power rail, and a fourth power rail disposed on the semiconductor substrate, extending in a first direction, and arranged sequentially in a second direction substantially perpendicular to the first direction;
• and
• at least one clock gate line disposed on the semiconductor substrate, and extending in the second direction to pass through at least two regions among a first region between the first power rail and the second power rail, a second region between the second power rail and the third power rail, and a third region between the third power rail and the fourth power rail,
• wherein the at least one clock gate line receives an input clock signal,
• wherein the semi-dynamic flip-flop comprises:
• a first circuit configured to generate a first feedback signal based on an input data signal, the input clock signal, a scan enable signal, a scan input signal, and a second feedback signal;
• a second circuit configured to generate the second feedback signal and a latch input signal based on the input data signal, the input clock signal, the scan enable signal, and the first feedback signal;
• and
• an output circuit configured to generate an output signal corresponding to the input data signal or the scan input signal based on the input clock signal and the latch input signal.

A semi-dynamic flip-flop, comprising:

• a semiconductor substrate;
• a first power rail, a second power rail, a third power rail, and a fourth power rail disposed on the semiconductor substrate, extending in a first direction, and arranged sequentially in a second direction substantially perpendicular to the first direction;
• and
• a first clock gate line and a second clock gate line disposed on the semiconductor substrate,
• wherein
• each of the first and second clock gate lines receives an input clock signal,
• the first clock gate line extends in the second direction to pass through a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail,
• the second clock gate line extends in the second direction to pass through the second region and a third region between the third power rail and the fourth power rail, and
• the second clock gate line is adjacent to the first clock gate line in the first direction.