Level shifter

A level shifting system, comprising:

• a first inverter configured to receive an input signal in a first voltage domain and shift the input signal from the first voltage domain to a first output signal at a first output terminal in a second voltage domain higher than the first voltage domain in response to a logical high state of a first clock signal in the first voltage domain;
• a second inverter configured to receive a complement of the input signal and shift the complement of the input signal from the first voltage domain to a second output signal at a second output terminal in the second voltage domain in response to the logical high state of the first clock signal;
• a pair of NMOS sensing transistors including a first NMOS sensing transistor and a second NMOS sensing transistor having a common source terminal, wherein a drain terminal of the first NMOS sensing transistor is coupled to the first inverter, a gate terminal of the first NMOS sensing transistor is configured to receive the input signal, a drain terminal of the second NMOS sensing transistor is coupled to the second inverter, and a gate terminal of the second NMOS sensing transistor is configured to receive the complement of the input signal;
• a PMOS transistor coupled between the first output terminal and the second output terminal and having a gate terminal connected to receive the first clock signal in the first voltage domain, the PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the first clock signal;
• and
• a latch circuit configured to latch the second output signal in the second voltage domain in response to a second clock signal, wherein the second clock signal and the first clock signal are in phase with one another.

A level shifting method, comprising:

• receiving a first clock signal having a logic high state and a logic low state in a first voltage domain;
• equalizing a first output signal at a first output terminal and a second output signal at a second output terminal in response to the logic low state of the first clock signal, the first output signal and the second output signal being in a second voltage domain higher than the first voltage domain;
• receiving an input signal in the first voltage domain;
• and
• outputting the first output signal at the first output terminal and the second output signal at the second output terminal based on the input signal and a complement of the input signal respectively in response to the logic high state of the first clock signal.