Flip flop circuit and data processing apparatus

A data processing apparatus, comprising:

• a flip flop circuit that comprises:
• a master latch circuit that comprises:
• a master output circuit configured to output master output data corresponding to master input data;
• and
• a master feedback circuit configured to feedback the master output data to an input side of the master output circuit, wherein
• the master latch circuit is configured to:
• receive the master input data based on target input data, and
• one of load or hold the master input data in response to a predetermined level change in a clock signal,
• the master latch circuit takes a master through state, based on a first level of the clock signal,
• in the master through state, the master latch circuit is further configured to generate the master output data on a basis of the master input data and first to N-th set signals, without the master output data from the master feedback circuit, N being an integer of 2 or larger,
• the master latch circuit further takes a master hold state based on a second level of the clock signal different from the first level of the clock signal, and
• in the master hold state, the master latch circuit is further configured to generate the master output data on a basis of the feedback master output data from the master feedback circuit regardless of the master input data;
• a slave latch circuit configured to one of load the master output data from the master latch circuit or hold the master output data;
• a data output section, wherein
• target output data, based on the target input data, is output from the data output section,
• the slave latch circuit includes first to N-th slave latch circuits,
• the first to N-th slave latch circuits are connected in parallel with each other,
• each slave latch circuit of the first to N-th slave latch circuits includes:
• a slave output circuit configured to:
• receive slave input data based on the master output data;
• and
• output slave output data corresponding to the slave input data;
• and
• a slave feedback circuit configured to feedback the slave output data to an input side of the slave output circuit,
• an i-th slave latch circuit of the first to N-th slave latch circuits takes a slave through state based on a first level of an i-th control signal of first to N-th control signals, i being an integer of 1 or larger and N or smaller,
• in the slave through state, the i-th slave latch circuit is configured to generate the slave output data on a basis of the slave input data and an i-th reset signal of first to N-th reset signals, without the slave output data from the slave feedback circuit;
• and
• an output selection circuit configured to select data output from one of the first to N-th slave latch circuits, wherein the selected data from the output selection circuit is output from the data output section as the target output data;
• a data input circuit configured to feed the target input data to the flip flop circuit;
• and
• a logic circuit configured to operate on a basis of the target output data output from the data output section of the flip flop circuit.

A data processing apparatus, comprising:

• a flip flop circuit that comprises:
• a master latch circuit that comprises:
• a master output circuit configured to output master output data corresponding to master input data;
• and
• a master feedback circuit configured to feedback the master output data to an input side of the master output circuit, wherein
• the master latch circuit is configured to:
• receive the master input data based on target input data, and
• one of load or hold the master input data in response to a predetermined level change in a clock signal,
• the master latch circuit takes a master through state, based on a first level of the clock signal,
• in the master through state, the master latch circuit is further configured to generate the master output data on a basis of the master input data and first to N-th set signals, without the master output data from the master feedback circuit, N being an integer of 2 or larger,
• the master latch circuit further takes a master hold state based on a second level of the clock signal different from the first level of the clock signal, and
• in the master hold state, the master latch circuit is further configured to generate the master output data on a basis of the feedback master output data from the master feedback circuit regardless of the master input data;
• a slave latch circuit configured to one of load the master output data from the master latch circuit or hold the master output data;
• a data output section, wherein
• target output data, based on the target input data, is output from the data output section,
• the slave latch circuit includes first to N-th slave latch circuits,
• the first to N-th slave latch circuits are connected in parallel with each other,
• each slave latch circuit of the first to N-th slave latch circuits includes:
• a slave output circuit configured to:
• receive slave input data based on the master output data;
• and
• output slave output data corresponding to the slave input data;
• and
• a slave feedback circuit configured to feedback the slave output data to an input side of the slave output circuit,
• an i-th slave latch circuit of the first to N-th slave latch circuits takes a slave through state based on a first level of an i-th control signal of first to N-th control signals, i being an integer of 1 or larger and N or smaller,
• in the slave through state, the i-th slave latch circuit is configured to generate the slave output data on a basis of the slave input data and an i-th reset signal of first to N-th reset signals, without the slave output data from the slave feedback circuit;
• an output selection circuit configured to select data output from one of the first to N-th slave latch circuits, wherein the selected data from the output selection circuit is output from the data output section as the target output data;
• a clock signal input section configured to receive an input of the clock signal including a rectangular wave signal;
• a clock selection signal input section configured to receive an input of a clock selection signal;
• an output selection signal input section configured to receive an input of an output selection signal;
• and
• a control signal generation circuit configured to generate the first to N-th control signals on a basis of the clock signal and the clock selection signal, wherein
• the master latch circuit is further configured to operate in synchronization with the clock signal,
• the output selection circuit is further configured to select one of the data output from the first to N-th slave latch circuits on a basis of the output selection signal;
• a data input circuit configured to feed the target input data to the flip flop circuit;
• a control circuit configured to feed the clock selection signal and the output selection signal to the flip flop circuit;
• and
• a logic circuit configured to operate on a basis of the target output data output from the data output section of the flip flop circuit.