US 11,057,022 B2 · PVT compensated delay cell for a monostable

Abstract

A monostable circuit includes a delay cell with a reference generator generating a reference current based upon a PVT invariant resistance and a threshold voltage, and a delay block with an output capacitor and an output circuit altering an amount of charge stored on the output capacitor as a function of the reference current, in response to an input signal. An inverter has an input coupled to the output circuit. A logic circuit logically combines output of the inverter and the input signal to generate a monostable trigger pulse. The output circuit includes a current source sourcing the reference current to the output capacitor in response to a first logic state of an input signal, and a current sink sinking current from the output capacitor to discharge the output capacitor, in response to a second logic state of the input signal.

Claims20

Dependent claims

A monostable circuit, comprising:

a delay cell, comprising:
a reference inverter having its input directly electrically connected to its output and configured to generate a threshold voltage;
a reference current generator configured to generate a reference current as a function of the threshold voltage and a process, voltage, and temperature (PVT) invariant resistance;
and
a delay block comprising:
an output capacitor;
and
an output circuit configured, in response to an input signal, to alter an amount of charge stored on the output capacitor as a function of the reference current;
a output inverter having an input coupled to the output circuit of the delay block and having an output;
and
a logic circuit configured to logically combine the output of the output inverter and the input signal to generate a monostable trigger pulse.

8 more elements

A monostable circuit, comprising:

a delay cell, comprising:
a reference inverter having its input coupled to its output and configured to generate a threshold voltage;
a reference current generator configured to generate a reference current as a function of the threshold voltage and a process, voltage, and temperature (PVT) invariant resistance;
and
a delay block comprising:
an output capacitor;
and
an output circuit configured, in response to an input signal, to alter an amount of charge stored on the output capacitor as a function of the reference current;
a output inverter having an input coupled to the output circuit of the delay block and having an output;
and
a logic circuit configured to logically combine the output of the output inverter and the input signal to generate a monostable trigger pulse;
wherein the output circuit of the delay block comprises:
a first p-channel transistor having a source coupled to receive the reference current, a drain, and a gate coupled to receive the input signal;
a second p-channel transistor having a source coupled to the source of the first p-channel transistor, a drain coupled to ground, and a gate coupled to receive a complement of the input signal;
and
an n-channel transistor having a drain coupled to the drain of the first p-channel transistor, a source coupled to ground, and a gate coupled to receive the input signal;
and
wherein the output capacitor is coupled between the drain of the n-channel transistor and ground.

15 more elements

A monostable circuit, comprising:

a delay cell, comprising:
a reference inverter having its input coupled to its output and configured to generate a threshold voltage;
a reference current generator configured to generate a reference current as a function of the threshold voltage and a process, voltage, and temperature (PVT) invariant resistance;
and
a delay block comprising:
an output capacitor;
and
an output circuit configured, in response to an input signal, to alter an amount of charge stored on the output capacitor as a function of the reference current;
a output inverter having an input coupled to the output circuit of the delay block and having an output;
and
a logic circuit configured to logically combine the output of the output inverter and the input signal to generate a monostable trigger pulse;
wherein the output circuit of the delay block comprises:
a first n-channel transistor having a source coupled to receive the reference current, a drain, and a gate coupled to receive the input signal;
a second n-channel transistor having a source coupled to the source of the first n-channel transistor, a drain coupled to a supply voltage, and a gate coupled to receive a complement of the input signal;
and
a p-channel transistor having a drain coupled to the drain of the first n-channel transistor, a source coupled to the supply voltage, and a gate coupled to receive the input signal;
and
wherein the output capacitor is coupled between the drain of the p-channel transistor and the supply voltage.

15 more elements

A delay cell, comprising:

a reference current generator configured to generate a reference current as a function of a threshold voltage and a process, voltage, and temperature (PVT) invariant resistance;
and
a delay block comprising:
an output capacitor;
and
an output circuit configured, in response to an input signal, to alter an amount of charge stored on the output capacitor as a function of the reference current;
wherein the PVT invariant resistance comprises:
a reference resistance generator configured to generate a reference resistance based upon a bandgap current and a bandgap voltage;
and
a replica resistance generator coupled to the reference resistance generator and configured to generate a resistance value for the PVT invariant resistance that is equal to a resistance value of the reference resistance.

7 more elements

Dependencies are inferred from the claim text.

PVT compensated delay cell for a monostable

Life of this patent

PVT compensated delay cell for a monostable

Life of this patent

Abstract

Claims20