Fixed latency configurable tap digital filter
AssigneeSchweitzer Engineering Laboratories, Inc.
InventorSrinivas Achanta
Life of this patent
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Abstract
A fixed latency configurable tap or fixed-tap digital filter may filter a signal in a fixed amount of time, regardless of the number of taps. The filter may include one or more of a clock, a plurality of registers in a shift register, an adder, an accumulator, and/or a scaler. In at least one embodiment, a running average may be maintained as samples are received such that the latency remains fixed with a constant number of clock cycles.
Claims20
A fixed latency digital filter with a selectable tap length, comprising:
- an input component to receive a timing signal that defines a sampling interval for the digital filter;
- a shift register with a number of registers equal to a selected tap length, including a first register, a plurality of intermediary registers, and a last register,
- wherein sampled values are sequentially shifted through the shift register, and
- wherein, for each sampling interval of the digital filter, the first register receives a new sampled value and shifts stored sampled values within the shift register, such that after a plurality of sampling intervals, each sampled value is shifted from the first register through the plurality of intermediary registers to the last register;
- an adder to generate a difference between a sampled value stored in the last register and a sampled value stored in the first register during each sampling interval;
- an accumulator that, for each sampling interval, generates an accumulation value by adding a difference generated by the adder during a previous sampling interval to a sum of prior differences generated by the adder;
- a scaler to generate a filtered value output by multiplying the accumulation value by 1/C, where C is a constant, and
- an output component to output the filtered value output.
A fixed latency digital filter with a selectable tap length, comprising:
- an input component to receive a timing signal defining a sampling period for the digital filter;
- a shift register having a number of registers with no less than a selected number of taps, wherein sampled values are sequentially shifted through the shift register from a first register through intermediary registers to a last register;
- an adder to generate a difference between sampled values stored in the first and last shift registers during each sampling interval;
- an accumulator that generates an accumulation value during each sampling period by adding a difference generated by the adder during a previous sampling period to a sum of prior differences generated by the adder;
- and
- an output component to output the accumulation value.
A method for generating a fixed latency filtered output via a configurable FIR filter, comprising:
- receiving a timing signal that defines a sampling period to be used by the configurable FIR filter;
- storing, in a shift register, sampled values in a number, N, of registers equal to the number, L, of selected taps in the configurable FIR filter;
- sequentially shifting sampled values through the shift register from a first register through intermediary registers to a last register;
- determining a difference, via an adder, between an oldest sampled value and a newest sampled value in the shift register at each Nth sampling interval;
- and
- determining an accumulation value by adding the difference determined by the difference adder at each Nth sampling interval to a summation of differences determined by the adder for a plurality of prior sampling intervals.
Dependencies are inferred from the claim text.