Amplifiers suitable for mm-wave signal splitting and combining

A multiple-input multiple-output amplifier circuit operable to couple each of a selected input port or a combination of input ports to each of a selected output port or a combination of output ports, the circuit comprising:

• N input transistors, N being greater than one, with each of the input transistors having its base or gate coupled to a respective one of N input port nodes, its emitter or source coupled to ground, and its collector or drain connected to an intermediate node, each input transistor enabling the respective one of the N input port nodes when its base or gate is biased and disabling the respective one of the N input port nodes when its base or gate is grounded;
• M output transistors, M being greater than one, with each of the output transistors having its base or gate coupled to a bias node, its emitter or source connected to the intermediate node, and its collector or drain coupled to a respective one of M output port nodes, each output transistor enabling the respective one of the M output port nodes when its bias node is asserted and disabling the respective one of the M output port nodes when its bias node is deasserted,
• where the base or gate of the input transistor for each enabled input port is biased to provide a quiescent current I0*m/n through that input transistor, where m is the number of enabled output ports and n is the number of enabled input ports, m and n being variable.

A method of coupling a selectable one of multiple input ports or a combination of said multiple input ports to a selectable one of multiple output ports or a combination of said multiple output ports, the method comprising:

• for each of the multiple input ports, coupling the base or gate of an input transistor to a corresponding input port node, an emitter or source of that input transistor to ground, and a collector or drain of that input transistor to an intermediate node;
• for each of the multiple output ports, coupling the base or gate of an output transistor to a corresponding bias node, an emitter or source of that output transistor to the intermediate node, and the collector or drain of that output transistor to a corresponding output port node;
• switchably coupling the bias nodes to a bias voltage and a ground, respectively, to enable and disable the corresponding output port node;
• switchably biasing the base or gate of each input transistor to an adjustable bias voltage and a ground, respectively, to enable and disable the corresponding input port node;
• and
• causing the adjustable bias voltage to provide an adjustable quiescent current through each enabled input transistor, the adjustable quiescent current being I0*m/n, where m is the number of enabled output ports and n is the number of enabled input ports, m and n being variable.