Snapback clamps for ESD protection with voltage limited, centralized triggering scheme
AssigneeNXP USA, Inc.
InventorsMichael A. Stockinger, Marcin Grad, Paul Hendrik Cappon, Sjoerd Bruinsma
Life of this patent
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Abstract
An apparatus for electrostatic discharge protection. In one embodiment, an integrated circuit (IC) includes a trigger circuit configured to generate a trigger voltage VT in response to an electrostatic discharge (ESD) event. A plurality of metal oxide semiconductor (MOS) transistors are coupled to the trigger circuit. The plurality of MOS transistors are configured to conduct ESD current from a plurality of circuit nodes, respectively, to a ground conductor in response to the trigger circuit generating the trigger voltage VT. A voltage limiter circuit is also included and is configured to limit the trigger voltage VT.
Claims20
An integrated circuit (IC) comprising:
- a trigger circuit configured to generate a trigger voltage VT in response to an electrostatic discharge (ESD) event;
- a plurality of metal oxide semiconductor (MOS) transistors coupled to the trigger circuit, wherein the plurality of MOS transistors are configured to conduct ESD current from a plurality of circuit nodes, respectively, to a first conductor in response to the trigger circuit generating the trigger voltage VT;
- a voltage limiter circuit configured to limit the trigger voltage VT.
An integrated circuit (IC) comprising:
- a trigger circuit configured to generate a trigger voltage VT in response to an electrostatic discharge (ESD) event;
- a plurality of metal oxide semiconductor (MOS) transistors coupled to the trigger circuit, wherein the plurality of MOS transistors are configured to conduct ESD current from a plurality of circuit nodes, respectively, to a first conductor in response to the trigger circuit generating the trigger voltage VT;
- a conductor configured to provide the trigger voltage VT to substrate bodies of the plurality of MOS transistors.
An integrated circuit (IC) comprising:
- a first pad configured to receive a signal;
- a first MOS transistor coupled to the first pad, wherein the first MOS transistor is configured to transition to snapback mode when voltage at the first pad exceeds a snapback trigger threshold for the first MOS transistor;
- a second MOS transistor coupled to a first conductor, wherein the second MOS transistor is configured to transition to snapback mode when voltage at the first conductor exceeds a snapback trigger voltage threshold for the second MOS transistor;
- a trigger circuit configured to generate a trigger voltage VT for lowering the first MOS transistor's snapback trigger voltage threshold and for lowering the second MOS transistor's snapback trigger voltage threshold;
- a voltage limiter configured to limit the trigger voltage VT.
Dependencies are inferred from the claim text.