Bus structure for parallel connected power switches

An apparatus comprising:

• a plurality of semiconductor switches, wherein first and second semiconductor switches of the plurality of semiconductor switches are housed in respective first and second semiconductor packages;
• a first bus directly connected to and interconnecting first terminals of the semiconductor switches in a first chain and provides a first impedance between adjacent ones of the first terminals in the first chain;
• and
• a second bus directly connected to and interconnecting second terminals of the semiconductor switches in a second chain and providing a second impedance greater that the first impedance between adjacent ones of the second terminals in the second chain, wherein the second bus comprises respective separate flat connection plates disposed on respective ones of the first and second semiconductor packages and at least one conductive bridge interconnecting the connection plates.

An apparatus comprising:

• a planar array of semiconductor switch packages comprising first and second semiconductor switch packages arranged in a first row, each of the first and second semiconductor switch packages comprising a semiconductor switch having first and second terminals and
• third and fourth semiconductor switch packages arranged in a second row parallel to the first row, each of the third and fourth semiconductor switch packages comprising a semiconductor switch having first and second terminals;
• and
• a laminated bus bar assembly disposed on one side of the planar array of semiconductor switch packages and comprising first, second and third overlapping plates, wherein:
• the first plate interconnects the first terminals of the first and second semiconductor switch packages and provides a first impedance therebetween;
• the second plate interconnects the first terminals of the third and fourth semiconductor switch packages and provides a second impedance therebetween;
• and
• the third plate has a first subregion electrically connected to the second terminals of the first and third semiconductor switch packages, a second subregion electrically connected to the second terminals of the second and fourth semiconductor switch packages, and at least one feature between the first and second subregions that provides a third impedance between the second terminals of the first and second semiconductor switch packages and between the second terminals of the third and fourth semiconductor switch packages that is greater than the first and second impedances.