Memory device having programmable impedance elements with a common conductor formed below bit lines

An integrated circuit (IC) device, comprising:

• a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction;
• a plurality of two-terminal programmable impedance elements formed over the substrate arranged into groups, each programmable impedance element programmable between at least two different impedance values;
• a plurality of conductive plate structures, each formed on and having a common conductive connection to a different group of the programmable impedance elements, each group comprising multiple rows and columns of programmable impedance elements, each conductive plate structure extending in at least the first direction;
• a plurality of storage contacts, each storage contact extending from a first current terminal of each access transistor to one of the programmable impedance elements;
• a plurality of bit lines formed over the conductive plate structures, the bit lines extending in a second direction different from the first direction;
• and
• a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the conductive plate structures to one of the bit lines;
• wherein
• the access transistors and programmable impedance elements form memory cells that each include no more than one impedance element.

An integrated circuit (IC) device, comprising:

• a plurality of bit lines extending in a first direction;
• at least one conductive plate structure formed between the bit lines and a substrate and extending in a second direction different from the first direction;
• a plurality of two-terminal programmable impedance elements arranged into rows and columns and having a common conductive connection to the at least one conductive plate structure, each programmable impedance element programmable between at least two different impedance values;
• a plurality of access transistors formed in the substrate having control terminals connected to word lines that extend in the second direction;
• a plurality of bit line contacts that each extend from one of the bit lines through an opening in the at least one conductive plate structure to a first current terminal of one of the access transistors;
• and
• a plurality of storage contacts that each extend from one programmable impedance element to a second current terminal of one of the corresponding access transistors;
• and
• each access transistor and its one corresponding programmable impedance element form one memory cell.